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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2022 12:48:44.7313 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ebb2e75-05f6-4d09-24c4-08da455f6533 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3448 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add lwm(Limit WaterMark) field to Rxq object which indicates the percentage of RX queue size used by HW to raise LWM event to the user. Allow LWM setting in modify_rq command. Allow the LWM configuration dynamically by adding RDY2RDY state change. Signed-off-by: Spike Du --- drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_devx.c | 13 ++++++++++++- drivers/net/mlx5/mlx5_devx.h | 1 + drivers/net/mlx5/mlx5_rx.h | 1 + 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index ef755ee..305edff 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1395,6 +1395,7 @@ enum mlx5_rxq_modify_type { MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ + MLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */ }; enum mlx5_txq_modify_type { diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 4b48f94..c918a50 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -62,7 +62,7 @@ * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ -static int +int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type) { struct mlx5_devx_modify_rq_attr rq_attr; @@ -76,6 +76,11 @@ case MLX5_RXQ_MOD_RST2RDY: rq_attr.rq_state = MLX5_RQC_STATE_RST; rq_attr.state = MLX5_RQC_STATE_RDY; + if (rxq->lwm) { + rq_attr.modify_bitmask |= + MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM; + rq_attr.lwm = rxq->lwm; + } break; case MLX5_RXQ_MOD_RDY2ERR: rq_attr.rq_state = MLX5_RQC_STATE_RDY; @@ -85,6 +90,12 @@ rq_attr.rq_state = MLX5_RQC_STATE_RDY; rq_attr.state = MLX5_RQC_STATE_RST; break; + case MLX5_RXQ_MOD_RDY2RDY: + rq_attr.rq_state = MLX5_RQC_STATE_RDY; + rq_attr.state = MLX5_RQC_STATE_RDY; + rq_attr.modify_bitmask |= MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM; + rq_attr.lwm = rxq->lwm; + break; default: break; } diff --git a/drivers/net/mlx5/mlx5_devx.h b/drivers/net/mlx5/mlx5_devx.h index a95207a..ebd1da4 100644 --- a/drivers/net/mlx5/mlx5_devx.h +++ b/drivers/net/mlx5/mlx5_devx.h @@ -11,6 +11,7 @@ int mlx5_txq_devx_modify(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type, uint8_t dev_port); void mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj); +int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type); extern struct mlx5_obj_ops devx_obj_ops; diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index e715ed6..25a5f2c 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -175,6 +175,7 @@ struct mlx5_rxq_priv { struct mlx5_devx_rq devx_rq; struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ uint32_t hairpin_status; /* Hairpin binding status. */ + uint32_t lwm:16; }; /* External RX queue descriptor. */ -- 1.8.3.1