From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 45E0CA034C; Sat, 4 Jun 2022 18:27:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 282DD42B79; Sat, 4 Jun 2022 18:27:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B868842B76 for ; Sat, 4 Jun 2022 18:27:40 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254FrqRj032131; Sat, 4 Jun 2022 09:27:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=VUtZ4VxKZVQoAK4fpZRoQc0ITnRteO8IkPr9jnMqwbU=; b=HbuXiKrd1nuXWIPzJkc9npz3Nq5PqYxvDSZa5SciAu5xpPGn/Tn2a8nxTVAxHbko2Urj AMvPgkID6C4ch4R8UouOC3Hnb1tCRMPmvkUrFPdzjMCl0/82S2Sfbx7KKpxcmK5ggWMB BjL20qOVU5lQU+e8iT9teqrecYMa5cmKAeqx4ITtklKcF2h8iECEXSKc/Fe1kNWB4Sua R8CoZKdw7c3Sdh9SXYo0syRVcM2h9XUf2/L6TqAYuXQOXSzRtZive22vpxeh4pn96DOy V0kVgeKLQvHdYDE66j1r9ploFWnzlxHBnWBADRywSDrtgWH73A/OnU7jowDCE7WTnH4X kg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3gg9ndg4hc-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 04 Jun 2022 09:27:39 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 4 Jun 2022 09:27:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 4 Jun 2022 09:27:38 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id AE2E33F70AB; Sat, 4 Jun 2022 09:27:35 -0700 (PDT) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Jakub Palider , "Tomasz Duszynski" CC: , Subject: [PATCH 09/10] common/cnxk: sync eth mode change command with firmware Date: Sat, 4 Jun 2022 18:26:50 +0200 Message-ID: <20220604162651.3503338-10-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: inFZzCT0MH2QUQzKnT_INerRlCIhsQxw X-Proofpoint-GUID: inFZzCT0MH2QUQzKnT_INerRlCIhsQxw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Layout of eth mode change command defined by firmware has been changed recently. So in order to retain compatibility between ROC and firmware update existing codebase. Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_bphy_cgx.c | 11 +++++++-- drivers/common/cnxk/roc_bphy_cgx.h | 19 +++++++++++++- drivers/common/cnxk/roc_bphy_cgx_priv.h | 12 +++++---- drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 4 +++ drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 33 +++++++++++++++++++++++++ 5 files changed, 71 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index 4b62905164..a5df104088 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -367,8 +367,10 @@ roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, { uint64_t scr1, scr0; - if (roc_model_is_cn10k()) + if (roc_model_is_cn9k() && + (mode->use_portm_idx || mode->portm_idx || mode->mode_group_idx)) { return -ENOTSUP; + } if (!roc_cgx) return -EINVAL; @@ -383,7 +385,12 @@ roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) | FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) | FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) | - FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_USE_PORTM_IDX, + mode->use_portm_idx) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORTM_IDX, + mode->portm_idx) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE_GROUP_IDX, + mode->mode_group_idx) | FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode)); return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index 3b645eb130..4ce1316513 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -72,13 +72,30 @@ enum roc_bphy_cgx_eth_link_mode { ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT, ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT, ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50GBASE_CR2_C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50GBASE_KR2_C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100GBASE_CR2_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100GBASE_KR2_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_SFI_1G_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25GBASE_CR_C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25GBASE_KR_C_BIT, __ROC_BPHY_CGX_ETH_LINK_MODE_MAX }; +enum roc_bphy_cgx_mode_group { + ROC_BPHY_CGX_MODE_GROUP_ETH, +}; + struct roc_bphy_cgx_link_mode { bool full_duplex; bool an; - unsigned int port; + bool use_portm_idx; + unsigned int portm_idx; + enum roc_bphy_cgx_mode_group mode_group_idx; enum roc_bphy_cgx_eth_link_speed speed; enum roc_bphy_cgx_eth_link_mode mode; }; diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index c8c406439c..78fa1eaa6b 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -74,11 +74,13 @@ enum eth_cmd_own { #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8) /* struct eth_mode_change_args */ -#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8) -#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12) -#define SCR1_ETH_MODE_CHANGE_ARGS_AN BIT_ULL(13) -#define SCR1_ETH_MODE_CHANGE_ARGS_PORT GENMASK_ULL(21, 14) -#define SCR1_ETH_MODE_CHANGE_ARGS_MODE GENMASK_ULL(63, 22) +#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8) +#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12) +#define SCR1_ETH_MODE_CHANGE_ARGS_AN BIT_ULL(13) +#define SCR1_ETH_MODE_CHANGE_ARGS_USE_PORTM_IDX BIT_ULL(14) +#define SCR1_ETH_MODE_CHANGE_ARGS_PORTM_IDX GENMASK_ULL(19, 15) +#define SCR1_ETH_MODE_CHANGE_ARGS_MODE_GROUP_IDX GENMASK_ULL(21, 20) +#define SCR1_ETH_MODE_CHANGE_ARGS_MODE GENMASK_ULL(63, 22) /* struct eth_set_fec_args */ #define SCR1_ETH_SET_FEC_ARGS GENMASK_ULL(9, 8) diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index de1c372334..f839a70f04 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -112,6 +112,10 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, memset(&rlink_mode, 0, sizeof(rlink_mode)); rlink_mode.full_duplex = link_mode->full_duplex; rlink_mode.an = link_mode->autoneg; + rlink_mode.use_portm_idx = link_mode->use_portm_idx; + rlink_mode.portm_idx = link_mode->portm_idx; + rlink_mode.mode_group_idx = + (enum roc_bphy_cgx_mode_group)link_mode->mode_group_idx; rlink_mode.speed = (enum roc_bphy_cgx_eth_link_speed)link_mode->speed; rlink_mode.mode = diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index 86e58e4756..7f326e3643 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -143,14 +143,47 @@ enum cnxk_bphy_cgx_eth_link_mode { CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT, /** 100GBASE-KR4 */ CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT, + /** 50GAUI-2-C2C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2C_BIT, + /** 50GAUI-2-C2M */ + CNXK_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2M_BIT, + /** 50GBASE-CR2-C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_50GBASE_CR2_C_BIT, + /** 50GBASE-KR2-C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_50GBASE_KR2_C_BIT, + /** 100GAUI-2-C2C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2C_BIT, + /** 100GAUI-2-C2M */ + CNXK_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2M_BIT, + /** 100GBASE-CR2 */ + CNXK_BPHY_CGX_ETH_LINK_MODE_100GBASE_CR2_BIT, + /** 100GBASE-KR2 */ + CNXK_BPHY_CGX_ETH_LINK_MODE_100GBASE_KR2_BIT, + /** SFI-1G */ + CNXK_BPHY_CGX_ETH_LINK_MODE_SFI_1G_BIT, + /** 25GBASE-CR-C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_25GBASE_CR_C_BIT, + /** 25GBASE-KR-C */ + CNXK_BPHY_CGX_ETH_LINK_MODE_25GBASE_KR_C_BIT, __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX }; +enum cnxk_bphy_cgx_mode_group { + /** ETH group */ + CNXK_BPHY_CGX_MODE_GROUP_ETH, +}; + struct cnxk_bphy_cgx_msg_link_mode { /** Setting for full-duplex */ bool full_duplex; /** Setting for automatic link negotiation */ bool autoneg; + /** Set to true to use port index */ + bool use_portm_idx; + /** Port index */ + unsigned int portm_idx; + /** Mode group */ + enum cnxk_bphy_cgx_mode_group mode_group_idx; /** Link speed */ enum cnxk_bphy_cgx_eth_link_speed speed; /** Link mode */ -- 2.25.1