From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 799A0A034C; Sat, 4 Jun 2022 18:28:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 05BCD427F6; Sat, 4 Jun 2022 18:27:46 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 148F6427F6 for ; Sat, 4 Jun 2022 18:27:43 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254G5RAU012809; Sat, 4 Jun 2022 09:27:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Fxa0moYnHln5wo0mTnbFnCe0kvLrfXf49zYwpYDL+AY=; b=eidO/poSVDr1I6e91FGWJ8qvV3newSzy4XHB+nRL4c7Kp8xXp7BjPTcpzBIMo2wWtzKr Qt6qWWb3/NHhAgfZXNmQDjuzhrQYB7Z8x9TsYnGVKIzYzoeZV7V0gQ1VZUVO4u/Ai3kT 10rE9AenSTftim0SbiDso4LaJ7H+8WqfdMTDD+gqnLWMhGdrNE4LrE4NKweUdCggPps4 Ji8i+9hd8x6uxyFmKh9x8NW/pggR27wiRHcgkeFsCVrQP1gSoi8dmJQMuMYUHihZhR6B 3pBeYd62Gs5+23kJqVVKWMEcPwHVP6i+/Gdv1edW/zbSWQDN9k8+Me4pki3lCYhipbec 0w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gg6wq0dhh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 04 Jun 2022 09:27:43 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 4 Jun 2022 09:27:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 4 Jun 2022 09:27:41 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id C9DB13F7097; Sat, 4 Jun 2022 09:27:38 -0700 (PDT) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Jakub Palider , "Tomasz Duszynski" CC: , Subject: [PATCH 10/10] common/cnxk: support switching CPRI/ETH back and forth Date: Sat, 4 Jun 2022 18:26:51 +0200 Message-ID: <20220604162651.3503338-11-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: rHifoJjZBoOWYgTxIjPT2cAqihU_RoA7 X-Proofpoint-GUID: rHifoJjZBoOWYgTxIjPT2cAqihU_RoA7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for toggling modes between ETH and CPRI on newer MACs (RPM). Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_bphy_cgx.h | 17 ++++++++++++++++- drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 14 ++++++++++++-- drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 27 +++++++++++++++++++++++++-- 3 files changed, 53 insertions(+), 5 deletions(-) diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index 4ce1316513..2b9a23f5b1 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -86,8 +86,20 @@ enum roc_bphy_cgx_eth_link_mode { __ROC_BPHY_CGX_ETH_LINK_MODE_MAX }; +/* Supported CPRI modes */ +enum roc_bphy_cgx_eth_mode_cpri { + ROC_BPHY_CGX_ETH_MODE_CPRI_2_4G_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_3_1G_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_4_9G_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_6_1G_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_9_8G_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_10_1_BIT, + ROC_BPHY_CGX_ETH_MODE_CPRI_24_3G_BIT, +}; + enum roc_bphy_cgx_mode_group { ROC_BPHY_CGX_MODE_GROUP_ETH, + ROC_BPHY_CGX_MODE_GROUP_CPRI = 2, }; struct roc_bphy_cgx_link_mode { @@ -97,7 +109,10 @@ struct roc_bphy_cgx_link_mode { unsigned int portm_idx; enum roc_bphy_cgx_mode_group mode_group_idx; enum roc_bphy_cgx_eth_link_speed speed; - enum roc_bphy_cgx_eth_link_mode mode; + union { + enum roc_bphy_cgx_eth_link_mode mode; + enum roc_bphy_cgx_eth_mode_cpri mode_cpri; + }; }; struct roc_bphy_cgx_link_info { diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index f839a70f04..26def43564 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -118,8 +118,18 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, (enum roc_bphy_cgx_mode_group)link_mode->mode_group_idx; rlink_mode.speed = (enum roc_bphy_cgx_eth_link_speed)link_mode->speed; - rlink_mode.mode = - (enum roc_bphy_cgx_eth_link_mode)link_mode->mode; + switch (link_mode->mode_group_idx) { + case CNXK_BPHY_CGX_MODE_GROUP_ETH: + rlink_mode.mode = + (enum roc_bphy_cgx_eth_link_mode) + link_mode->mode; + break; + case CNXK_BPHY_CGX_MODE_GROUP_CPRI: + rlink_mode.mode_cpri = + (enum roc_bphy_cgx_eth_mode_cpri) + link_mode->mode_cpri; + break; + } ret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode); break; case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE: diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index 7f326e3643..f9949fa313 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -168,9 +168,28 @@ enum cnxk_bphy_cgx_eth_link_mode { __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX }; +enum cnxk_bphy_cgx_eth_mode_cpri { + /** 2.4G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_2_4G_BIT, + /** 3.1G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_3_1G_BIT, + /** 4.9G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_4_9G_BIT, + /** 6.1G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_6_1G_BIT, + /** 9.8G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_9_8G_BIT, + /** 10.1G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_10_1_BIT, + /** 24.3G Lane Rate */ + CNXK_BPHY_CGX_ETH_MODE_CPRI_24_3G_BIT, +}; + enum cnxk_bphy_cgx_mode_group { /** ETH group */ CNXK_BPHY_CGX_MODE_GROUP_ETH, + /** CPRI group */ + CNXK_BPHY_CGX_MODE_GROUP_CPRI = 2, }; struct cnxk_bphy_cgx_msg_link_mode { @@ -186,8 +205,12 @@ struct cnxk_bphy_cgx_msg_link_mode { enum cnxk_bphy_cgx_mode_group mode_group_idx; /** Link speed */ enum cnxk_bphy_cgx_eth_link_speed speed; - /** Link mode */ - enum cnxk_bphy_cgx_eth_link_mode mode; + union { + /** Link mode */ + enum cnxk_bphy_cgx_eth_link_mode mode; + /** CPRI mode */ + enum cnxk_bphy_cgx_eth_mode_cpri mode_cpri; + }; }; struct cnxk_bphy_cgx_msg_link_info { -- 2.25.1