From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 00A73A034C; Sat, 4 Jun 2022 18:27:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D7E5041155; Sat, 4 Jun 2022 18:27:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 1A072410D5 for ; Sat, 4 Jun 2022 18:27:16 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254GRF5u032547; Sat, 4 Jun 2022 09:27:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=/0gmQBGeSSIBtiTkbYSHlXBh8hh+1AMWC5JbKIx3qP0=; b=JQMjXbZjERLd9g/n9HSIWsxkBL9RqYq3jgs1/seGPL8EoAgQAJ3SrOYNphAkkYvelbmo lX6ZHLYml0vo6NeZnbkizMNhLQ+asIFiZE1jg0B5ETNn/nk+zCnxjpmszMtVsZVl6RJZ q18R62P2QmLhXyTIVUzANbp+cIAf9vyB1hoMSGy6+MZTwtSG9Un2vajo5zgaZlOnPIeA 4ozLY6AFPmbblezsjdSi7NCDsoDABRV5fIegCGnxfobbSy+BNb91JG3zGGlHm48/MYaX qzMyDzrZQc125MraBuXlTy2L3daMiMiHnxm+F5lfx3I/Bluz0ZzZ/Y9m39SYDn7Awu6t Jw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gg6wq0dgt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 04 Jun 2022 09:27:15 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 4 Jun 2022 09:27:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 4 Jun 2022 09:27:13 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id E4BC53F70AB; Sat, 4 Jun 2022 09:27:10 -0700 (PDT) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Tomasz Duszynski , Jakub Palider Subject: [PATCH 01/10] common/cnxk: update register access for CNF10xxN Date: Sat, 4 Jun 2022 18:26:42 +0200 Message-ID: <20220604162651.3503338-2-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: OH569jmjlkaBeG1N0VhHsAaF7B5mx9IR X-Proofpoint-GUID: OH569jmjlkaBeG1N0VhHsAaF7B5mx9IR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Due to HW changes some fields which were used to enable xmit were moved elsewhere. This patch takes care of this. Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran Tested-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_bphy_cgx.c | 33 ++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index c3be3c9041..19baaa6757 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -21,10 +21,13 @@ * * Hence common longer mask may be used. */ -#define CGX_CMRX_RX_LMACS 0x128 -#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0) -#define CGX_CMRX_SCRATCH0 0x1050 -#define CGX_CMRX_SCRATCH1 0x1058 +#define CGX_CMRX_RX_LMACS 0x128 +#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0) +#define CGX_CMRX_SCRATCH0 0x1050 +#define CGX_CMRX_SCRATCH1 0x1058 +#define CGX_MTI_MAC100X_COMMAND_CONFIG 0x8010 +#define CGX_MTI_MAC100X_COMMAND_CONFIG_RX_ENA BIT_ULL(1) +#define CGX_MTI_MAC100X_COMMAND_CONFIG_TX_ENA BIT_ULL(0) static uint64_t roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset) @@ -221,7 +224,7 @@ static int roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, bool start) { - uint64_t val; + uint64_t val, reg, rx_field, tx_field; if (!roc_cgx) return -EINVAL; @@ -229,16 +232,24 @@ roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) return -ENODEV; + if (roc_model_is_cnf10kb()) { + reg = CGX_MTI_MAC100X_COMMAND_CONFIG; + rx_field = CGX_MTI_MAC100X_COMMAND_CONFIG_RX_ENA; + tx_field = CGX_MTI_MAC100X_COMMAND_CONFIG_TX_ENA; + } else { + reg = CGX_CMRX_CONFIG; + rx_field = CGX_CMRX_CONFIG_DATA_PKT_RX_EN; + tx_field = CGX_CMRX_CONFIG_DATA_PKT_TX_EN; + } + pthread_mutex_lock(&roc_cgx->lock); - val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_CONFIG); - val &= ~(CGX_CMRX_CONFIG_DATA_PKT_RX_EN | - CGX_CMRX_CONFIG_DATA_PKT_TX_EN); + val = roc_bphy_cgx_read(roc_cgx, lmac, reg); + val &= ~(rx_field | tx_field); if (start) - val |= FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_RX_EN, 1) | - FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_TX_EN, 1); + val |= FIELD_PREP(rx_field, 1) | FIELD_PREP(tx_field, 1); - roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_CONFIG, val); + roc_bphy_cgx_write(roc_cgx, lmac, reg, val); pthread_mutex_unlock(&roc_cgx->lock); return 0; -- 2.25.1