From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3A10A034C; Sat, 4 Jun 2022 18:27:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CFC9542B6C; Sat, 4 Jun 2022 18:27:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7860742802 for ; Sat, 4 Jun 2022 18:27:24 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254FrHf3030275; Sat, 4 Jun 2022 09:27:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=xUeP9GW2sneb/ayTg0EJaeq7K1mjwvCAkacovcaTUDU=; b=VgbWqUR7yz9z4avK0yoYYVRFu9G7S9xKN0ZGGRK1e1pcpOfU2TRQJpW4WinFItcNrbqC IxTc7M40nD7Fl+06HEe3EDs6qh558HazLlQlQo+ALyXS2ZnclmcFfyWulTAJZD9UlO6s qM97grw6TV6xDflQjjHEzgtJuGVYWhus6h3An/lhBvfMf0mJQxqUPGMlHsx92rPa1Y0U 0xx8gVWIAqp4bH2sT5aou6Djb3AANFhChxESyoej68Rhv3fvhe2NrYnyns/LvmJanmci Wr2B6bi6wz+JAx8v91Qxk5tl5kMfWYOktnk5PMVtmT1mrBO2NVkBO4Rjb6vkjMNlgvsm 0A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3gg9ndg4gf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 04 Jun 2022 09:27:23 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 4 Jun 2022 09:27:22 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 4 Jun 2022 09:27:22 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 615623F7097; Sat, 4 Jun 2022 09:27:19 -0700 (PDT) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Tomasz Duszynski , Jakub Palider Subject: [PATCH 04/10] common/cnxk: don't switch affinity back and forth Date: Sat, 4 Jun 2022 18:26:45 +0200 Message-ID: <20220604162651.3503338-5-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: uB29Bo8-6_OEmh1UQrmrgB79MLvoXGXT X-Proofpoint-GUID: uB29Bo8-6_OEmh1UQrmrgB79MLvoXGXT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Switching affinity back and forth was used as a mean to pass cpu number to irq registration routine which is an overkill. Simplify current logic by extending irq registration routine parameter list with a cpu which should run irq handler. Signed-off-by: Tomasz Duszynski Reviewed-by: Jakub Palider Reviewed-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_bphy_irq.c | 103 +++-------------------------- 1 file changed, 9 insertions(+), 94 deletions(-) diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c index f4954d2a28..7b39b61537 100644 --- a/drivers/common/cnxk/roc_bphy_irq.c +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -11,8 +11,6 @@ #include "roc_api.h" #include "roc_bphy_irq.h" -#define roc_cpuset_t cpu_set_t - struct roc_bphy_irq_usr_data { uint64_t isr_base; uint64_t sp; @@ -222,14 +220,13 @@ roc_bphy_intr_handler(unsigned int irq_num) } static int -roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, +roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int cpu, int irq_num, void (*isr)(int irq_num, void *isr_data), void *isr_data) { - roc_cpuset_t orig_cpuset, intr_cpuset; struct roc_bphy_irq_usr_data irq_usr; const struct plt_memzone *mz; - int i, retval, curr_cpu, rc; + int retval, rc; char *env; mz = plt_memzone_lookup(chip->mz_name); @@ -244,38 +241,11 @@ roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, if (chip->irq_vecs[irq_num].handler != NULL) return -EINVAL; - rc = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (rc < 0) { - plt_err("Failed to get affinity mask"); - return rc; - } - - for (curr_cpu = -1, i = 0; i < CPU_SETSIZE; i++) - if (CPU_ISSET(i, &orig_cpuset)) - curr_cpu = i; - if (curr_cpu < 0) - return -ENOENT; - - CPU_ZERO(&intr_cpuset); - CPU_SET(curr_cpu, &intr_cpuset); - rc = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), - &intr_cpuset); - if (rc < 0) { - plt_err("Failed to set affinity mask"); - return rc; - } - irq_usr.isr_base = (uint64_t)roc_bphy_intr_handler; - irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(curr_cpu); - irq_usr.cpu = curr_cpu; - if (irq_usr.sp == 0) { - rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (rc < 0) - plt_err("Failed to restore affinity mask"); - return rc; - } + irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(cpu); + irq_usr.cpu = cpu; + if (irq_usr.sp == 0) + return -ENOMEM; /* On simulator memory locking operation takes much time. We want * to skip this when running in such an environment. @@ -289,23 +259,18 @@ roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, *((struct roc_bphy_irq_chip **)(mz->addr)) = chip; irq_usr.irq_num = irq_num; - chip->irq_vecs[irq_num].handler_cpu = curr_cpu; + chip->irq_vecs[irq_num].handler_cpu = cpu; chip->irq_vecs[irq_num].handler = isr; chip->irq_vecs[irq_num].isr_data = isr_data; retval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr); if (retval != 0) { - roc_bphy_irq_stack_remove(curr_cpu); + roc_bphy_irq_stack_remove(cpu); chip->irq_vecs[irq_num].handler = NULL; chip->irq_vecs[irq_num].handler_cpu = -1; } else { chip->n_handlers++; } - rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (rc < 0) - plt_warn("Failed to restore affinity mask"); - return retval; } @@ -327,7 +292,6 @@ roc_bphy_intr_max_get(struct roc_bphy_irq_chip *irq_chip) int roc_bphy_intr_clear(struct roc_bphy_irq_chip *chip, int irq_num) { - roc_cpuset_t orig_cpuset, intr_cpuset; const struct plt_memzone *mz; int retval; @@ -343,24 +307,6 @@ roc_bphy_intr_clear(struct roc_bphy_irq_chip *chip, int irq_num) if (mz == NULL) return -ENXIO; - retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (retval < 0) { - plt_warn("Failed to get affinity mask"); - CPU_ZERO(&orig_cpuset); - CPU_SET(0, &orig_cpuset); - } - - CPU_ZERO(&intr_cpuset); - CPU_SET(chip->irq_vecs[irq_num].handler_cpu, &intr_cpuset); - retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), - &intr_cpuset); - if (retval < 0) { - plt_warn("Failed to set affinity mask"); - CPU_ZERO(&orig_cpuset); - CPU_SET(0, &orig_cpuset); - } - retval = ioctl(chip->intfd, ROC_BPHY_IOC_CLR_BPHY_HANDLER, irq_num); if (retval == 0) { roc_bphy_irq_stack_remove(chip->irq_vecs[irq_num].handler_cpu); @@ -378,14 +324,6 @@ roc_bphy_intr_clear(struct roc_bphy_irq_chip *chip, int irq_num) plt_err("Failed to clear bphy interrupt handler"); } - retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (retval < 0) { - plt_warn("Failed to restore affinity mask"); - CPU_ZERO(&orig_cpuset); - CPU_SET(0, &orig_cpuset); - } - return retval; } @@ -393,36 +331,13 @@ int roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip, struct roc_bphy_intr *intr) { - roc_cpuset_t orig_cpuset, intr_cpuset; - int retval; int ret; if (!roc_bphy_intr_available(irq_chip, intr->irq_num)) return -ENOTSUP; - retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (retval < 0) { - plt_err("Failed to get affinity mask"); - return retval; - } - - CPU_ZERO(&intr_cpuset); - CPU_SET(intr->cpu, &intr_cpuset); - retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), - &intr_cpuset); - if (retval < 0) { - plt_err("Failed to set affinity mask"); - return retval; - } - - ret = roc_bphy_irq_handler_set(irq_chip, intr->irq_num, + ret = roc_bphy_irq_handler_set(irq_chip, intr->cpu, intr->irq_num, intr->intr_handler, intr->isr_data); - retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), - &orig_cpuset); - if (retval < 0) - plt_warn("Failed to restore affinity mask"); - return ret; } -- 2.25.1