From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 03040A034C; Sat, 4 Jun 2022 18:29:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3BECF427F3; Sat, 4 Jun 2022 18:29:39 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 40701427F2 for ; Sat, 4 Jun 2022 18:29:37 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254GFNCM005477; Sat, 4 Jun 2022 09:27:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=dWhmKrCjobjsF7q6naehW9rbPivSCIGdzGKFNChJWqk=; b=iET1OTr4O/gAk432YqWC9nEd7n+gl39Rcd7IqvzWOTlr6x0HE+QccZ1FxGgidDaGQinS IZvKuhDcnfMtW8H/YfBWN6aTrVtgyEI9gZhe6nG2dFB209xZumLOynX/G9XSId6FtHwW b4tq8dUjcxjCx6XEvm2HtlJVvXguMn/px3cuTdUW3oKQRGwm9IzGBZ52M0Y/ctWVwJK8 gVYFnNqCMFL8otRhGSLb+9FgcTVZgk5MOzaPta0Ekwe2i25yw/R2Fc/04J2EUSy+xTdg +5UtHT2OPZcOoByegBC7JttWoUwfKTSkFvlf0OUMBtf7CVSiO/yGH1LkhaxYL8frwSxs jw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gg6wq0dhc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 04 Jun 2022 09:27:34 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 4 Jun 2022 09:27:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 4 Jun 2022 09:27:32 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 3DE793F70AB; Sat, 4 Jun 2022 09:27:29 -0700 (PDT) From: Tomasz Duszynski To: , Jakub Palider , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Subject: [PATCH 07/10] raw/cnxk_bphy: support changing CPRI misc settings Date: Sat, 4 Jun 2022 18:26:48 +0200 Message-ID: <20220604162651.3503338-8-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220604162651.3503338-1-tduszynski@marvell.com> References: <20220604162651.3503338-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: gS2DYty29RYNYpyn-GvrkU78JGzcjwI2 X-Proofpoint-GUID: gS2DYty29RYNYpyn-GvrkU78JGzcjwI2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for changing miscellaneous CPRI settings. Signed-off-by: Tomasz Duszynski Reviewed-by: Jerin Jacob Kollanukkaran --- doc/guides/rawdevs/cnxk_bphy.rst | 11 ++++++++ drivers/common/cnxk/roc_bphy_cgx.c | 30 +++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 8 ++++++ drivers/common/cnxk/roc_bphy_cgx_priv.h | 6 +++++ drivers/common/cnxk/version.map | 1 + drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 10 +++++++ drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 36 +++++++++++++++++++++++++ 7 files changed, 102 insertions(+) diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst index 50ee9bdaa6..2490912534 100644 --- a/doc/guides/rawdevs/cnxk_bphy.rst +++ b/doc/guides/rawdevs/cnxk_bphy.rst @@ -121,6 +121,17 @@ Prior to sending actual message payload i.e ``struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl`` needs to be filled with relevant information. +Change CPRI misc settings +~~~~~~~~~~~~~~~~~~~~~~~~~ + +Message is used to change misc CPRI settings, for example to reset RX state +machine on CPRI SERDES. + +Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC``. +Prior to sending actual message payload i.e +``struct cnxk_bphy_cgx_msg_cpri_mode_misc`` needs to be filled with relevant +information. + BPHY PMD -------- diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index ee0198924e..4b62905164 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -519,3 +519,33 @@ roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); } + +int +roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_cpri_mode_misc *mode) +{ + uint64_t scr1, scr0; + + if (!(roc_model_is_cnf95xxn_a0() || + roc_model_is_cnf95xxn_a1() || + roc_model_is_cnf95xxn_b0())) + return -ENOTSUP; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -ENODEV; + + if (!mode) + return -EINVAL; + + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_MISC) | + FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX, + mode->gserc_idx) | + FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX, + mode->lane_idx) | + FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_FLAGS, mode->flags); + + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); +} diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index b8023cce88..3b645eb130 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -106,6 +106,12 @@ struct roc_bphy_cgx_cpri_mode_tx_ctrl { bool enable; }; +struct roc_bphy_cgx_cpri_mode_misc { + int gserc_idx; + int lane_idx; + int flags; +}; + __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); @@ -138,5 +144,7 @@ __roc_api int roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsign struct roc_bphy_cgx_cpri_mode_change *mode); __roc_api int roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode); +__roc_api int roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_cpri_mode_misc *mode); #endif /* _ROC_BPHY_CGX_H_ */ diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index 96db34f6a1..a1a4239cbe 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -71,6 +71,7 @@ enum eth_cmd_id { ETH_CMD_SET_PTP_MODE = 34, ETH_CMD_CPRI_MODE_CHANGE = 35, ETH_CMD_CPRI_TX_CONTROL = 36, + ETH_CMD_CPRI_MISC = 42, }; /* event types - cause of interrupt */ @@ -147,6 +148,11 @@ enum eth_cmd_own { #define SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX GENMASK_ULL(15, 12) #define SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE BIT_ULL(16) +/* struct cpri_mode_misc_args */ +#define SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX GENMASK_ULL(11, 8) +#define SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX GENMASK_ULL(15, 12) +#define SCR1_CPRI_MODE_MISC_ARGS_FLAGS GENMASK_ULL(17, 16) + #define SCR1_OWN_STATUS GENMASK_ULL(1, 0) #endif /* _ROC_BPHY_CGX_PRIV_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index a6183799a9..d5fd1f41c2 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -29,6 +29,7 @@ INTERNAL { roc_ae_fpm_put; roc_aes_xcbc_key_derive; roc_bphy_cgx_cpri_mode_change; + roc_bphy_cgx_cpri_mode_misc; roc_bphy_cgx_cpri_mode_tx_control; roc_bphy_cgx_dev_fini; roc_bphy_cgx_dev_init; diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index bdc65a7f2a..de1c372334 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -59,10 +59,12 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, struct cnxk_bphy_cgx_msg_cpri_mode_change *cpri_mode; struct cnxk_bphy_cgx_msg_set_link_state *link_state; struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *tx_ctrl; + struct cnxk_bphy_cgx_msg_cpri_mode_misc *mode_misc; struct cnxk_bphy_cgx_msg *msg = buf->buf_addr; struct cnxk_bphy_cgx_msg_link_mode *link_mode; struct cnxk_bphy_cgx_msg_link_info *link_info; struct roc_bphy_cgx_cpri_mode_change rcpri_mode; + struct roc_bphy_cgx_cpri_mode_misc rmode_misc; struct roc_bphy_cgx_cpri_mode_tx_ctrl rtx_ctrl; struct roc_bphy_cgx_link_info rlink_info; struct roc_bphy_cgx_link_mode rlink_mode; @@ -159,6 +161,14 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, ret = roc_bphy_cgx_cpri_mode_tx_control(cgx->rcgx, lmac, &rtx_ctrl); break; + case CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC: + mode_misc = msg->data; + memset(&rmode_misc, 0, sizeof(rmode_misc)); + rmode_misc.gserc_idx = mode_misc->gserc_idx; + rmode_misc.lane_idx = mode_misc->lane_idx; + rmode_misc.flags = mode_misc->flags; + ret = roc_bphy_cgx_cpri_mode_misc(cgx->rcgx, lmac, &rmode_misc); + break; default: return -EINVAL; } diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index 79bb2233bc..86e58e4756 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -54,6 +54,8 @@ enum cnxk_bphy_cgx_msg_type { CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE, /** Type used to enable TX for CPRI SERDES */ CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL, + /** Type use to change misc CPRI SERDES settings */ + CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC, }; /** Available link speeds */ @@ -197,6 +199,15 @@ struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl { bool enable; }; +struct cnxk_bphy_cgx_msg_cpri_mode_misc { + /** SERDES index (0 - 4) */ + int gserc_idx; + /** Lane index (0 - 1) */ + int lane_idx; + /** Misc flags (0 - RX Eq, 1 - RX state machine reset) */ + int flags; +}; + struct cnxk_bphy_cgx_msg { /** Message type */ enum cnxk_bphy_cgx_msg_type type; @@ -770,6 +781,31 @@ rte_pmd_bphy_cgx_cpri_tx_control(uint16_t dev_id, uint16_t lmac, return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); } +/** + * CPRI misc settings + * + * @param dev_id + * The identifier of the device + * @param lmac + * LMAC number for operation + * @param mode + * CPRI settings holding misc control data + * + * @return + * Returns 0 on success, negative error code otherwise + */ +static __rte_always_inline int +rte_pmd_bphy_cgx_cpri_mode_misc(uint16_t dev_id, uint16_t lmac, + struct cnxk_bphy_cgx_msg_cpri_mode_misc *mode) +{ + struct cnxk_bphy_cgx_msg msg = { + .type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC, + .data = mode, + }; + + return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); +} + #ifdef __cplusplus } #endif -- 2.25.1