From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0E3ADA034C; Sat, 4 Jun 2022 18:32:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EA02B4021E; Sat, 4 Jun 2022 18:32:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7E4BD40041 for ; Sat, 4 Jun 2022 18:32:14 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 254G5RAc012809; Sat, 4 Jun 2022 09:32:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=QBUci6xR4AyQZOXUhTsS/tPlTBJn48ZhvrLHFxSQnpg=; b=VBYJ6iwKtpoq+g0yyOL8zwBqO+OwoLkJ2nBYKY/gGXNeu9xE4JuE3TC1m+mpUWpkoE4H OB3U4NRwt8XyRxr513sSi+R0aynLh5MmPyzSUTbZ2C1stwMXHCRt9fNckcBmikmi8gXa xtDLrJXXkvS7VQIPQWbnif2xejEjX7C+cc04w2dXjbCJ7kaGhrbsMq5NRX1l3crExkWc JOLlvnazIzwwouJFDDJJ++yCQV+bG7X/pAT779H1ZF3aEpTv2/Ro621gdQ7FsK07xbed rtHUCbwnJo5p+ekYZScVNMv/zuCfqE3nCtHiGtd0JgSZgsiymsFq7/XF3wVRNnQQcCWk LA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gg6wq0dsy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 04 Jun 2022 09:32:13 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 4 Jun 2022 09:32:11 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 4 Jun 2022 09:32:11 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id B80083F70AC; Sat, 4 Jun 2022 09:32:08 -0700 (PDT) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Pavan Nikhilesh , "Shijith Thotton" CC: , , Tomasz Duszynski Subject: [PATCH] common/cnxk: allow building generic arm64 target for cn9k/cn10k Date: Sat, 4 Jun 2022 18:31:57 +0200 Message-ID: <20220604163157.3509505-1-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: H4aEnzq51P558-AMVh7GXOb_8V5z0BT- X-Proofpoint-GUID: H4aEnzq51P558-AMVh7GXOb_8V5z0BT- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allow building generic arm64 target using config/arm/arm64_armv8_linux_* config which works on both cn9k and cn10k by relaxing cache line size requirements a bit. While at it move cache line checks to common place. Signed-off-by: Tomasz Duszynski Reviewed-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_dev.c | 26 ++++++++++++++++++++++++++ drivers/event/cnxk/cn10k_eventdev.c | 5 ----- drivers/event/cnxk/cn9k_eventdev.c | 5 ----- drivers/net/cnxk/cn10k_ethdev.c | 5 ----- drivers/net/cnxk/cn9k_ethdev.c | 5 ----- 5 files changed, 26 insertions(+), 20 deletions(-) diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c index 9a869698c4..09199ac2ff 100644 --- a/drivers/common/cnxk/roc_dev.c +++ b/drivers/common/cnxk/roc_dev.c @@ -1094,6 +1094,29 @@ dev_lmt_setup(struct dev *dev) return -errno; } +static bool +dev_cache_line_size_valid(void) +{ + if (roc_model_is_cn9k()) { + if (PLT_CACHE_LINE_SIZE != 128) { + plt_err("Cache line size of %d is wrong for CN9K", + PLT_CACHE_LINE_SIZE); + return false; + } + } else if (roc_model_is_cn10k()) { + if (PLT_CACHE_LINE_SIZE == 128) { + plt_warn("Cache line size of %d might affect performance", + PLT_CACHE_LINE_SIZE); + } else if (PLT_CACHE_LINE_SIZE != 64) { + plt_err("Cache line size of %d is wrong for CN10K", + PLT_CACHE_LINE_SIZE); + return false; + } + } + + return true; +} + int dev_init(struct dev *dev, struct plt_pci_device *pci_dev) { @@ -1102,6 +1125,9 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev) uintptr_t vf_mbase = 0; uint64_t intr_offset; + if (!dev_cache_line_size_valid()) + return -EFAULT; + bar2 = (uintptr_t)pci_dev->mem_resource[2].addr; bar4 = (uintptr_t)pci_dev->mem_resource[4].addr; if (bar2 == 0 || bar4 == 0) { diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 77f0c28160..25d01fd90a 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -963,11 +963,6 @@ cn10k_sso_init(struct rte_eventdev *event_dev) struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); int rc; - if (RTE_CACHE_LINE_SIZE != 64) { - plt_err("Driver not compiled for CN10K"); - return -EFAULT; - } - rc = roc_plt_init(); if (rc < 0) { plt_err("Failed to initialize platform model"); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 4d45f02c1c..6fef15e352 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -1193,11 +1193,6 @@ cn9k_sso_init(struct rte_eventdev *event_dev) struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); int rc; - if (RTE_CACHE_LINE_SIZE != 128) { - plt_err("Driver not compiled for CN9K"); - return -EFAULT; - } - rc = roc_plt_init(); if (rc < 0) { plt_err("Failed to initialize platform model"); diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 4cd82af7e5..33f61743f9 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -759,11 +759,6 @@ cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) struct cnxk_eth_dev *dev; int rc; - if (RTE_CACHE_LINE_SIZE != 64) { - plt_err("Driver not compiled for CN10K"); - return -EFAULT; - } - rc = roc_plt_init(); if (rc) { plt_err("Failed to initialize platform model, rc=%d", rc); diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c index a388b3a8a6..fb34d20759 100644 --- a/drivers/net/cnxk/cn9k_ethdev.c +++ b/drivers/net/cnxk/cn9k_ethdev.c @@ -689,11 +689,6 @@ cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) struct cnxk_eth_dev *dev; int rc; - if (RTE_CACHE_LINE_SIZE != 128) { - plt_err("Driver not compiled for CN9K"); - return -EFAULT; - } - rc = roc_plt_init(); if (rc) { plt_err("Failed to initialize platform model, rc=%d", rc); -- 2.25.1