From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9FB40A0543; Mon, 6 Jun 2022 13:22:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B801A427F3; Mon, 6 Jun 2022 13:21:58 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2057.outbound.protection.outlook.com [40.107.223.57]) by mails.dpdk.org (Postfix) with ESMTP id 19642415D7 for ; Mon, 6 Jun 2022 13:21:57 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jwPD8++7UBdYf9nhunqYO82BoZkcumtHfuvIzo95Xp/Ujs25cFBoxVcesRKT7x23ca1MNbjkf6aahKSDqXJxZwzp+rUrETa7HHoJ4IKIht/rKAfJkrzmXbneghChZANpuEjhnWKMr832aVTgZDlvd2o4A/hWQvyP2V+lSxEaUyHlV/GULOxktaPLSZcEdlHoe3EEp9ATzzIJpyrdS5bR3cgQBneEjKARzy2fccN4HDXI8xllfZ7YA7iUopLP0cwNGoOY0CK5Ze46FEl/Tu7vxchwjTqazCHxevODmAbWIXfA53D3P3BPOEtlBvnJPlqYGv4XkFsgfOhfJ9noky6Vhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=We/bsNcpSpBekIWDvBf9E+epWgYn0d2hG5xm0p+Apr4=; b=ST0h/rvc1ChMt1QFlUEWqHcxhz36b9TnjlJ5w5B1Job1v/dcnHkLOWn5nZw2M54LIvndHJ66wR7fhAFaFYN/OBVf1Y4uaOC/OdBnfLlaVrPxlSh28Kcb7SI2A5uF8TfAmQ0gFcBta3FpDl7hTkrgQAz3V6WtTZA+vtgee9cWVs6oRWjmCkCi38YnBi+my/NW5fG7xn7g3uFO+lqrppMN7Qxfu/huJAiUoB6qk/fdna9jAwAt9TIs90J2k/pIwvR4OXrl3/6D/CTKavS7vRd3LYcwqIM3vq33a7tBIJXP5oK8L1PpUbV6Meq/miqsDXslhJOYECRtoJsR3o6bLsVr3w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=We/bsNcpSpBekIWDvBf9E+epWgYn0d2hG5xm0p+Apr4=; b=D3uxj62lRSVYYHPRlYz392KsR15lt6LehVKI8esSDgvmf/QwaJThJTnhVA8ZuhfH1MYjoYx8qDpTxHitW4VHEivCmvCTPbudOTfYVCgvvi+mpXhC2X8j8Ir46sz2hcoLYfsAEIP37OzuBjWgWNfEQcCYfHPsjSOhqYyjDaBACvU/syJH+Ni0zR4z28XfgieFECD4+n5Pam5ZJ7v+k7SZ8eeHQa/sWuuUnSC0BTlu+iGizObRLSR3VH758s/AZi/QOoj4I8OEQpHehg0pWr0SH4h0M9VHqOtCMpV3PZzKuBOb2ger8vHNs9Qzha3tTCCQscwcpzUTA8baSV3BhC0hbg== Received: from MWHPR18CA0029.namprd18.prod.outlook.com (2603:10b6:320:31::15) by BN9PR12MB5067.namprd12.prod.outlook.com (2603:10b6:408:134::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.12; Mon, 6 Jun 2022 11:21:55 +0000 Received: from CO1NAM11FT015.eop-nam11.prod.protection.outlook.com (2603:10b6:320:31:cafe::3d) by MWHPR18CA0029.outlook.office365.com (2603:10b6:320:31::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.19 via Frontend Transport; Mon, 6 Jun 2022 11:21:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.234) by CO1NAM11FT015.mail.protection.outlook.com (10.13.175.130) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Mon, 6 Jun 2022 11:21:55 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 6 Jun 2022 11:21:54 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 6 Jun 2022 04:21:51 -0700 From: Li Zhang To: , , , CC: , , , , Yajun Wu Subject: [PATCH 04/16] common/mlx5: add DevX API to move QP to reset state Date: Mon, 6 Jun 2022 14:20:43 +0300 Message-ID: <20220606112109.208873-7-lizh@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606112109.208873-1-lizh@nvidia.com> References: <20220408075606.33056-1-lizh@nvidia.com> <20220606112109.208873-1-lizh@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: af6e4e7c-5fc0-4bc0-bb4a-08da47aec34c X-MS-TrafficTypeDiagnostic: BN9PR12MB5067:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FuNKHvQpcd1zLTQT4sUK4kfx/UytIqoLZb9P1mug8tfRRzJomXljvdWM1zzym6V1iDzQED/g1rEsa5E8yYwzPBDA8mXrd8YvOA9dbeMSa6lEJ17xlqvWRI8SeMkpkcxCtdpqdfbFcS9XZWxPeBMHnkmXIroklz3LWP/KvBl5hfiGjUvcrb//S3+ue88YrKzQZUkvdLuoTKhz7Dj+BwEg6EtanFt+6lUBKhcydV0rM7JatWKGKjpcyw8/AvjdhHgQuuiplnJVAaBxMgrAoxXJD5GtgEyOhobZ2kfsyIWNVxSmiGdE7KCzgdclxFHr/+mCEVt6rZasV/W7Q5iSEYdwKZ7VXJwe4lYjTYmsgfUErkI4gyb4ZbGPaTMHWYsw4mDnG7w6nP85lCvIJ8JoGZkjh/uWUVnGiq8b0kcYJ4FctkaAmjsJgOA/JdxKq29hYJ8NLsP66VRcHYsRHHwgzk13+LV7xNfOV8FJRuqu7aIR5T4b3HDM4WVjj4kpGXZFvjmC9cv45Dzs1LiRg5IDQU3LJsZQTCUiBBefBFaU5R3DfZnYSF61GrIA34ttStuMpVApAXMCUsnD7bFSqFnhvwy/tC7jfrtyMDQG/iHBVet5K8iG1ZRh/oR1/VJc6q6CvQFwOOXGCGKX8s8lET23Mgwiv711TR+EaV/qfnAxqM7v/Rq4XaU3+hoi55FBYPemd3Rkd7Ebqs+LlCegiVN6zrNSmw== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(426003)(6666004)(86362001)(508600001)(336012)(2906002)(316002)(55016003)(107886003)(40460700003)(1076003)(47076005)(186003)(16526019)(2616005)(6636002)(54906003)(110136005)(26005)(6286002)(7696005)(5660300002)(36756003)(36860700001)(8676002)(81166007)(8936002)(4326008)(356005)(70586007)(70206006)(82310400005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:21:55.1720 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af6e4e7c-5fc0-4bc0-bb4a-08da47aec34c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5067 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Yajun Wu Support set QP to RESET state. Signed-off-by: Yajun Wu --- drivers/common/mlx5/mlx5_devx_cmds.c | 7 +++++++ drivers/common/mlx5/mlx5_prm.h | 17 +++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index c6bdbc12bb..1d6d6578d6 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -2264,11 +2264,13 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; + uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; } in; union { uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; + uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; } out; void *qpc; int ret; @@ -2311,6 +2313,11 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, inlen = sizeof(in.rtr2rts); outlen = sizeof(out.rtr2rts); break; + case MLX5_CMD_OP_QP_2RST: + MLX5_SET(2rst_qp_in, &in, qpn, qp->id); + inlen = sizeof(in.qp2rst); + outlen = sizeof(out.qp2rst); + break; default: DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", qp_st_mod_op); diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index bc3e70a1d1..8a2f55c33e 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3657,6 +3657,23 @@ struct mlx5_ifc_init2init_qp_in_bits { u8 reserved_at_800[0x80]; }; +struct mlx5_ifc_2rst_qp_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_2rst_qp_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 vhca_tunnel_id[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_80[0x8]; + u8 qpn[0x18]; + u8 reserved_at_a0[0x20]; +}; + struct mlx5_ifc_dealloc_pd_out_bits { u8 status[0x8]; u8 reserved_0[0x18]; -- 2.31.1