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From: Min Zhou <zhoumin@loongson.cn>
To: thomas@monjalon.net, david.marchand@redhat.com,
	bruce.richardson@intel.com, anatoly.burakov@intel.com,
	qiming.yang@intel.com, Yuying.Zhang@intel.com,
	jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru
Cc: dev@dpdk.org, maobibo@loongson.cn
Subject: [v3 19/24] test/xmmt_ops: add dummy vector implementation for LoongArch
Date: Mon,  6 Jun 2022 21:10:49 +0800	[thread overview]
Message-ID: <20220606131054.2097526-20-zhoumin@loongson.cn> (raw)
In-Reply-To: <20220606131054.2097526-1-zhoumin@loongson.cn>

The hardware instructions based vector implementation will come
in a future patch. This dummy implementation can also work.

Signed-off-by: Min Zhou <zhoumin@loongson.cn>
---
 app/test/test_xmmt_ops.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h
index 3a82d5ecac..7b2c3c37dd 100644
--- a/app/test/test_xmmt_ops.h
+++ b/app/test/test_xmmt_ops.h
@@ -49,6 +49,23 @@ vect_set_epi32(int i3, int i2, int i1, int i0)
 	return data;
 }
 
+#elif defined(RTE_ARCH_LOONGARCH)
+/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
+static __rte_always_inline xmm_t
+vect_loadu_sil128(void *p)
+{
+	xmm_t data;
+	data = *(const xmm_t *)p;
+	return data;
+}
+
+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
+static __rte_always_inline xmm_t
+vect_set_epi32(int i3, int i2, int i1, int i0)
+{
+	xmm_t data = (xmm_t){.u32 = {i0, i1, i2, i3} };
+	return data;
+}
 #endif
 
 #endif /* _TEST_XMMT_OPS_H_ */
-- 
2.31.1


  parent reply	other threads:[~2022-06-06 13:11 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-06 13:10 [v3 00/24] Support LoongArch architecture Min Zhou
2022-06-06 13:10 ` [v3 01/24] eal/loongarch: add atomic operations for LoongArch Min Zhou
2022-07-20 10:16   ` zhoumin
2022-06-06 13:10 ` [v3 02/24] eal/loongarch: add byte order " Min Zhou
2022-06-06 13:10 ` [v3 03/24] eal/loongarch: add cpu cycle " Min Zhou
2022-06-06 13:10 ` [v3 04/24] eal/loongarch: add prefetch " Min Zhou
2022-06-06 13:10 ` [v3 05/24] eal/loongarch: add spinlock " Min Zhou
2022-06-06 13:10 ` [v3 06/24] eal/loongarch: add cpu flag checks " Min Zhou
2022-06-06 13:10 ` [v3 07/24] eal/loongarch: add dummy vector memcpy " Min Zhou
2022-06-06 13:10 ` [v3 08/24] eal/loongarch: add io operations " Min Zhou
2022-06-06 13:10 ` [v3 09/24] eal/loongarch: add mcslock " Min Zhou
2022-06-06 13:10 ` [v3 10/24] eal/loongarch: add pause " Min Zhou
2022-06-06 13:10 ` [v3 11/24] eal/loongarch: add pflock " Min Zhou
2022-06-06 13:10 ` [v3 12/24] eal/loongarch: add rwlock " Min Zhou
2022-06-06 13:10 ` [v3 13/24] eal/loongarch: add ticketlock " Min Zhou
2022-06-06 13:10 ` [v3 14/24] eal/loongarch: add power " Min Zhou
2022-06-06 13:10 ` [v3 15/24] eal/loongarch: add hypervisor " Min Zhou
2022-06-06 13:10 ` [v3 16/24] mem: add huge page size definition " Min Zhou
2022-06-06 13:10 ` [v3 17/24] eal/linux: set eal base address " Min Zhou
2022-06-06 13:10 ` [v3 18/24] meson: introduce LoongArch architecture Min Zhou
2022-06-06 13:10 ` Min Zhou [this message]
2022-06-06 13:10 ` [v3 20/24] ixgbe: add dummy vector implementation for LoongArch Min Zhou
2022-06-06 13:10 ` [v3 21/24] i40e: " Min Zhou
2022-06-06 13:10 ` [v3 22/24] tap: add system call number " Min Zhou
2022-06-06 13:10 ` [v3 23/24] memif: " Min Zhou
2022-06-06 13:10 ` [v3 24/24] maintainers: claim responsibility " Min Zhou
2022-07-20 16:33 ` [v3 00/24] Support LoongArch architecture David Marchand
2022-07-21 10:33   ` zhoumin

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