From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4872BA0542; Mon, 6 Jun 2022 15:18:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EC93D4280B; Mon, 6 Jun 2022 15:18:15 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id C93034021E for ; Mon, 6 Jun 2022 15:18:11 +0200 (CEST) Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9BxieTe_J1imxwXAA--.64917S8; Mon, 06 Jun 2022 21:11:00 +0800 (CST) From: Min Zhou To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn Subject: [v3 06/24] eal/loongarch: add cpu flag checks for LoongArch Date: Mon, 6 Jun 2022 21:10:36 +0800 Message-Id: <20220606131054.2097526-7-zhoumin@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220606131054.2097526-1-zhoumin@loongson.cn> References: <20220606131054.2097526-1-zhoumin@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: AQAAf9BxieTe_J1imxwXAA--.64917S8 X-Coremail-Antispam: 1UD129KBjvJXoWxAF4rur1kKryUCr47WFy5twb_yoWrWrWUpa yfCFy5Xw48Xr12k3yxXayjgF1rCF1xGF47AasxCw4Yva9rG34UZwsYkF93WF45A3yUXrnI gayY93y29FyUZw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch uses aux vector software register to get CPU flags and add CPU flag checking support for LoongArch architecture. Signed-off-by: Min Zhou --- lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++++ lib/eal/loongarch/rte_cpuflags.c | 94 ++++++++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h create mode 100644 lib/eal/loongarch/rte_cpuflags.c diff --git a/lib/eal/loongarch/include/rte_cpuflags.h b/lib/eal/loongarch/include/rte_cpuflags.h new file mode 100644 index 0000000000..d9121a00a8 --- /dev/null +++ b/lib/eal/loongarch/include/rte_cpuflags.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_CPUFLAGS_LOONGARCH_H_ +#define _RTE_CPUFLAGS_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Enumeration of all CPU features supported + */ +enum rte_cpu_flag_t { + RTE_CPUFLAG_CPUCFG = 0, + RTE_CPUFLAG_LAM, + RTE_CPUFLAG_UAL, + RTE_CPUFLAG_FPU, + RTE_CPUFLAG_LSX, + RTE_CPUFLAG_LASX, + RTE_CPUFLAG_CRC32, + RTE_CPUFLAG_COMPLEX, + RTE_CPUFLAG_CRYPTO, + RTE_CPUFLAG_LVZ, + RTE_CPUFLAG_LBT_X86, + RTE_CPUFLAG_LBT_ARM, + RTE_CPUFLAG_LBT_MIPS, + /* The last item */ + RTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */ +}; + +#include "generic/rte_cpuflags.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_CPUFLAGS_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/rte_cpuflags.c b/lib/eal/loongarch/rte_cpuflags.c new file mode 100644 index 0000000000..4abcd0fdb3 --- /dev/null +++ b/lib/eal/loongarch/rte_cpuflags.c @@ -0,0 +1,94 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include "rte_cpuflags.h" + +#include +#include +#include +#include +#include + +/* Symbolic values for the entries in the auxiliary table */ +#define AT_HWCAP 16 +#define AT_HWCAP2 26 + +/* software based registers */ +enum cpu_register_t { + REG_NONE = 0, + REG_HWCAP, + REG_MAX +}; + +typedef uint32_t hwcap_registers_t[REG_MAX]; + +struct feature_entry { + uint32_t reg; + uint32_t bit; +#define CPU_FLAG_NAME_MAX_LEN 64 + char name[CPU_FLAG_NAME_MAX_LEN]; +}; + +#define FEAT_DEF(name, reg, bit) \ + [RTE_CPUFLAG_##name] = {reg, bit, #name}, + +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(CPUCFG, REG_HWCAP, 0) + FEAT_DEF(LAM, REG_HWCAP, 1) + FEAT_DEF(UAL, REG_HWCAP, 2) + FEAT_DEF(FPU, REG_HWCAP, 3) + FEAT_DEF(LSX, REG_HWCAP, 4) + FEAT_DEF(LASX, REG_HWCAP, 5) + FEAT_DEF(CRC32, REG_HWCAP, 6) + FEAT_DEF(COMPLEX, REG_HWCAP, 7) + FEAT_DEF(CRYPTO, REG_HWCAP, 8) + FEAT_DEF(LVZ, REG_HWCAP, 9) + FEAT_DEF(LBT_X86, REG_HWCAP, 10) + FEAT_DEF(LBT_ARM, REG_HWCAP, 11) + FEAT_DEF(LBT_MIPS, REG_HWCAP, 12) +}; + +/* + * Read AUXV software register and get cpu features for LoongArch + */ +static void +rte_cpu_get_features(hwcap_registers_t out) +{ + out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); +} + +/* + * Checks if a particular flag is available on current machine. + */ +int +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) +{ + const struct feature_entry *feat; + hwcap_registers_t regs = {0}; + + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return -ENOENT; + + feat = &rte_cpu_feature_table[feature]; + if (feat->reg == REG_NONE) + return -EFAULT; + + rte_cpu_get_features(regs); + return (regs[feat->reg] >> feat->bit) & 1; +} + +const char * +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) +{ + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return NULL; + return rte_cpu_feature_table[feature].name; +} + +void +rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics) +{ + memset(intrinsics, 0, sizeof(*intrinsics)); +} -- 2.31.1