From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3CDB6A0544; Tue, 7 Jun 2022 12:46:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DE03B41153; Tue, 7 Jun 2022 12:46:29 +0200 (CEST) Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by mails.dpdk.org (Postfix) with ESMTP id 0290940156 for ; Tue, 7 Jun 2022 12:46:27 +0200 (CEST) Received: by mail-lj1-f181.google.com with SMTP id 1so18725361ljp.8 for ; Tue, 07 Jun 2022 03:46:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Locn3X9N47qAITJLgIqRSvmqDqR6UUvkVOq9UMSVY4s=; b=mkbCMU6qbUh0mTf1qj7Es5S5I16fnz3+bQNozR5az7VWpWHxptC4PXYaVzPonJsJSD yWcIPKAP/yQqTD1YZJ7ia/LMx8qKSQ13XsUOhqQBal926PgKzOi1OF2oF4OGsn+gJRa+ Tq/N9VVaHz4c59ERXKDMVCRoxzUCXC00HgIYGE6zq+XgriO/lUGL90c0DxSWuxQkaN5n KCRxEHOfI1rKFZDxq7X3q9KAw+BSd8qBdOuXuVYfTPmlmA4rNNocG3pdf6z6IZdpNcW/ fAruTNNZg7XYkMSpYcuLDRfKRlk4GpjXaqa+b8ulEs4x+8TQ+gwR5tWgIkxjvLXTHZbv U6pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Locn3X9N47qAITJLgIqRSvmqDqR6UUvkVOq9UMSVY4s=; b=pOweKKur3H1khVYZp6DMGja8QS4usiYQROZQ0cT2h4/oVNuE6JzFY3dAv+/wkQzvY4 /Rt9+V82R9MNXRj4Y1bKipueS+lxf9rMvdD34jkNHN+BgHYBcGSe0qfiX7b3Ma5PO8vn SxDktlezYorTyceNXE41o4oiUJgKaZoOXmWa260B9ruWI+N63iu4uC7Rr12Dv/v5gQIx snUMSGdAH7s6hg8LFYIvq8tj/iJUZmqINQQ2PnkXYM1AZUTQd/iOssHlkkWKkGckiFRe kdhZnvVJi+cNgdYlSOHG7wsNDomXH6gg5QiQdnKXpBg2Vewox2EQZ7f7z1Vk5Y7Uv+EZ GqQg== X-Gm-Message-State: AOAM530zkoHefkecquNDw7zV5Yg2upzRd6WphGyMd3FzztkiLTaInLMD hxv2o6GRroO6CtyH4nxHHe8MIrYPRI1TmmNZ X-Google-Smtp-Source: ABdhPJw0hqWD2vMm7M32nFebdF09Gf3n5yH233euS+Cu4jjbZw/3uLwUqA4hrowN+MeNkkFEzmqvWw== X-Received: by 2002:a2e:a88a:0:b0:250:bf9c:7e7f with SMTP id m10-20020a2ea88a000000b00250bf9c7e7fmr53768258ljq.83.1654598787373; Tue, 07 Jun 2022 03:46:27 -0700 (PDT) Received: from localhost.localdomain (89-73-146-138.dynamic.chello.pl. [89.73.146.138]) by smtp.gmail.com with ESMTPSA id m16-20020a056512115000b00478f2f2f044sm3217272lfg.123.2022.06.07.03.46.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 03:46:26 -0700 (PDT) From: Stanislaw Kardach To: dev@dpdk.org Cc: Stanislaw Kardach , Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com Subject: [PATCH RESEND v4 0/8] Introduce support for RISC-V architecture Date: Tue, 7 Jun 2022 12:46:09 +0200 Message-Id: <20220607104617.153892-1-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org RESEND: To trigger CI as all dependent patches have been merged already. This patchset adds support for building and running DPDK on 64bit RISC-V architecture. The initial support targets rv64gc (rv64imafdc) ISA and was tested on SiFive Unmatched development board with the Freedom U740 SoC running Linux (freedom-u-sdk based kernel). I have tested this codebase using DPDK unit and perf tests as well as test-pmd, l2fwd and l3fwd examples. The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD. On the UIO side, since U740 does not have an IOMMU, I've used igb_uio, uio_pci_generic and vfio-pci noiommu drivers. Functional verification done using meson tests. fast-tests suite passing with the default config. PMD verification done using a Intel x520-DA2 NIC (ixgbe) and the test-pmd application. Packet transfer checked using all UIO drivers available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio. The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector operations. RISCV support is currently limited to Linux as the time measurement frequency discovery is tied to reading a device-tree node via procfs. Clang compilation currently not supported due to issues with missing relocation relaxation. Commit 1 introduces EAL and build system support for RISC-V architecture as well as documentation updates. Commits 2-5 add missing defines and stubs to enable RISC-V operation in non-EAL parts. Commit 6 adds RISC-V specific cpuflags test. Commits 7-8 add RISC-V build testing to test-meson-builds.sh and github CI. I appreciate Your comments and feedback. Best Regards, Stanislaw Kardach v4: - Update RISC-V cross-compilation docs to remove vendor-specific instructions and better match the Ubuntu environment. - Remove optional "fence" removal in the CYCLE and TIME counter reads as those are irrelevant compared to the cost of a firmware call that allowed such removal. The per-platform build-configuration is left in meson files for setting '-mtune' and reference for future platforms. - Update cross-files to specify PKG_CONFIG_LIBDIR instead of relying on the riscv64-linux-gnu-pkg-config wrapper which was removed from Ubuntu anyway. Also use sys_root properly instead of using c_args directly. - Note: rte_rdtsc handling is left as it was in v3: TIME counter default, CYCLE via compile-time option. This is mostly due to CYCLE being core-local with values differing among cores which causes timer_autotest to run overly long if it so happens that CYCLE on core 0 is ahead of other cores' CYCLEs. This makes TIME counter more stable for general usage. Since CYCLE read in userspace can be disabled by the kernel-mode (it isn't currently), the compile-time approach is taken, same as with Aarch64. - Added details on --no-huge tests failing in the known_issues.rst. - Additional notes on tests: - link_bonding_mode4_autotest succeeds and then dpdk-test fails with segmentation fault randomly when run directly (via DPDK_TEST env variable) with MALLOC_PERTURB_. This was not noticed in any other test suggesting that there is a race condition somewhere in the link_bonding PMD that leads to use-after-free (since MALLOC_PERTURB_ causes free() to re-initialize freed memory to a given value). - ipsec_perf_autotest currently does not check whether there is any crypto device available (as ipsec_autotest does) and therefore fails. v3: - Limit test-meson-builds.sh testing to a generic rv64gc configuration. Previous version was missing this change by mistake. v2: - Separate bug-fixes into separate series. - Prevent RV64_CSRR leak to API users. - Limit test-meson-builds.sh testing to a generic rv64gc configuration. - Clean-up release notes and fix style issues. [1] http://lists.infradead.org/pipermail/opensbi/2021-June/001219.html Michal Mazurek (2): eal: add initial support for RISC-V architecture test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach (6): net/ixgbe: enable vector stubs for RISC-V net/memif: set memfd syscall ID on RISC-V net/tap: set BPF syscall ID for RISC-V examples/l3fwd: enable RISC-V operation devtools: add RISC-V to test-meson-builds.sh ci: add RISCV64 cross compilation job .ci/linux-build.sh | 4 + .github/workflows/build.yml | 11 +- MAINTAINERS | 6 + app/test/test_cpuflags.c | 81 +++++++++++ app/test/test_xmmt_ops.h | 16 +++ config/meson.build | 2 + config/riscv/meson.build | 131 ++++++++++++++++++ config/riscv/riscv64_linux_gcc | 17 +++ config/riscv/riscv64_sifive_u740_linux_gcc | 20 +++ devtools/test-meson-builds.sh | 4 + doc/guides/contributing/design.rst | 2 +- .../linux_gsg/cross_build_dpdk_for_riscv.rst | 115 +++++++++++++++ doc/guides/linux_gsg/index.rst | 1 + doc/guides/nics/features.rst | 5 + doc/guides/nics/features/default.ini | 1 + doc/guides/nics/features/ixgbe.ini | 1 + doc/guides/rel_notes/known_issues.rst | 10 +- doc/guides/rel_notes/release_22_07.rst | 8 ++ drivers/net/i40e/meson.build | 6 + drivers/net/ixgbe/ixgbe_rxtx.c | 4 +- drivers/net/memif/rte_eth_memif.h | 2 + drivers/net/tap/tap_bpf.h | 2 + examples/l3fwd/l3fwd_em.c | 8 ++ examples/l3fwd/l3fwd_fib.c | 2 + lib/eal/riscv/include/meson.build | 23 +++ lib/eal/riscv/include/rte_atomic.h | 52 +++++++ lib/eal/riscv/include/rte_byteorder.h | 44 ++++++ lib/eal/riscv/include/rte_cpuflags.h | 55 ++++++++ lib/eal/riscv/include/rte_cycles.h | 101 ++++++++++++++ lib/eal/riscv/include/rte_io.h | 21 +++ lib/eal/riscv/include/rte_mcslock.h | 18 +++ lib/eal/riscv/include/rte_memcpy.h | 63 +++++++++ lib/eal/riscv/include/rte_pause.h | 31 +++++ lib/eal/riscv/include/rte_pflock.h | 17 +++ lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++ lib/eal/riscv/include/rte_prefetch.h | 50 +++++++ lib/eal/riscv/include/rte_rwlock.h | 44 ++++++ lib/eal/riscv/include/rte_spinlock.h | 67 +++++++++ lib/eal/riscv/include/rte_ticketlock.h | 21 +++ lib/eal/riscv/include/rte_vect.h | 55 ++++++++ lib/eal/riscv/meson.build | 11 ++ lib/eal/riscv/rte_cpuflags.c | 122 ++++++++++++++++ lib/eal/riscv/rte_cycles.c | 77 ++++++++++ lib/eal/riscv/rte_hypervisor.c | 13 ++ lib/eal/riscv/rte_power_intrinsics.c | 56 ++++++++ meson.build | 2 + 46 files changed, 1417 insertions(+), 7 deletions(-) create mode 100644 config/riscv/meson.build create mode 100644 config/riscv/riscv64_linux_gcc create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst create mode 100644 lib/eal/riscv/include/meson.build create mode 100644 lib/eal/riscv/include/rte_atomic.h create mode 100644 lib/eal/riscv/include/rte_byteorder.h create mode 100644 lib/eal/riscv/include/rte_cpuflags.h create mode 100644 lib/eal/riscv/include/rte_cycles.h create mode 100644 lib/eal/riscv/include/rte_io.h create mode 100644 lib/eal/riscv/include/rte_mcslock.h create mode 100644 lib/eal/riscv/include/rte_memcpy.h create mode 100644 lib/eal/riscv/include/rte_pause.h create mode 100644 lib/eal/riscv/include/rte_pflock.h create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h create mode 100644 lib/eal/riscv/include/rte_prefetch.h create mode 100644 lib/eal/riscv/include/rte_rwlock.h create mode 100644 lib/eal/riscv/include/rte_spinlock.h create mode 100644 lib/eal/riscv/include/rte_ticketlock.h create mode 100644 lib/eal/riscv/include/rte_vect.h create mode 100644 lib/eal/riscv/meson.build create mode 100644 lib/eal/riscv/rte_cpuflags.c create mode 100644 lib/eal/riscv/rte_cycles.c create mode 100644 lib/eal/riscv/rte_hypervisor.c create mode 100644 lib/eal/riscv/rte_power_intrinsics.c -- 2.30.2