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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2022 02:31:20.4852 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7c6c216f-f264-43a7-11c2-08da4f404c84 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0099 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Yajun Wu Support set QP to RESET state. Signed-off-by: Yajun Wu Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 7 +++++++ drivers/common/mlx5/mlx5_prm.h | 17 +++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index c6bdbc12bb..1d6d6578d6 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -2264,11 +2264,13 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; + uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; } in; union { uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; + uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; } out; void *qpc; int ret; @@ -2311,6 +2313,11 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, inlen = sizeof(in.rtr2rts); outlen = sizeof(out.rtr2rts); break; + case MLX5_CMD_OP_QP_2RST: + MLX5_SET(2rst_qp_in, &in, qpn, qp->id); + inlen = sizeof(in.qp2rst); + outlen = sizeof(out.qp2rst); + break; default: DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", qp_st_mod_op); diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index bc3e70a1d1..8a2f55c33e 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3657,6 +3657,23 @@ struct mlx5_ifc_init2init_qp_in_bits { u8 reserved_at_800[0x80]; }; +struct mlx5_ifc_2rst_qp_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_2rst_qp_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 vhca_tunnel_id[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_80[0x8]; + u8 qpn[0x18]; + u8 reserved_at_a0[0x20]; +}; + struct mlx5_ifc_dealloc_pd_out_bits { u8 status[0x8]; u8 reserved_0[0x18]; -- 2.30.2