From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B831AA00BE; Thu, 16 Jun 2022 11:24:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 34F8A42C09; Thu, 16 Jun 2022 11:24:43 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0EA1D4281E for ; Thu, 16 Jun 2022 11:24:40 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25G9D2kL009455 for ; Thu, 16 Jun 2022 02:24:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=bY1GWMwY9KtMji3c8ASSPLeIJgVMOBmDQMotX9C4EmM=; b=ZUGUC8JK9fKDstEnbCsDbFN5FwldyCfCgqRvA6jWyCENS+qA8bBAaOaay3InmsqaZSEp f9scGVLbHKFwQSN9znWdx7WL3exHbuZQQ2yRGpS2matE+UTzYRDAYlZGzhsB3Kk7gbx3 nAjVbWnKrUZTlTLQXf0EV3d91AfDtnoNmuvRHD7Xtl6o7OcoljfvDZ3v4yDlEfFgGhbW aZNsvsqV4NDe2LzUUdZiW3/SPALY6hT5AdjOCv7RZBhVJF29SE5a8A76XXih2+J0N9qZ rp18/+w8KVBdIfQZGvOmV4vYbJp9KcUSL1A4FNfGcKrCPrp3PEaChYVlC9XOSoot2fL5 xQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3gr1pmg1xh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 16 Jun 2022 02:24:40 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 16 Jun 2022 02:24:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 16 Jun 2022 02:24:38 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 85F423F7075; Thu, 16 Jun 2022 02:24:36 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH v2 05/12] common/cnxk: enhance CPT parse header dump Date: Thu, 16 Jun 2022 14:54:13 +0530 Message-ID: <20220616092420.17861-5-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220616092420.17861-1-ndabilpuram@marvell.com> References: <20220616070743.30658-1-ndabilpuram@marvell.com> <20220616092420.17861-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: vowPe6MAWn4E_KlatPGaBLb2x6nF1prB X-Proofpoint-GUID: vowPe6MAWn4E_KlatPGaBLb2x6nF1prB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-16_05,2022-06-15_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enhance CPT parse header dump to dump fragment info and swap pointers before printing. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_cpt_debug.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c index be6ddb5..5602e53 100644 --- a/drivers/common/cnxk/roc_cpt_debug.c +++ b/drivers/common/cnxk/roc_cpt_debug.c @@ -8,6 +8,10 @@ void roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth) { + struct cpt_frag_info_s *frag_info; + uint32_t offset; + uint64_t *slot; + plt_print("CPT_PARSE \t0x%p:", cpth); /* W0 */ @@ -19,7 +23,7 @@ roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth) cpth->w0.pad_len, cpth->w0.num_frags, cpth->w0.pkt_out); /* W1 */ - plt_print("W1: wqe_ptr \t0x%016lx\t", cpth->wqe_ptr); + plt_print("W1: wqe_ptr \t0x%016lx\t", plt_be_to_cpu_64(cpth->wqe_ptr)); /* W2 */ plt_print("W2: frag_age \t0x%x\t\torig_pf_func \t0x%04x", @@ -33,7 +37,32 @@ roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth) /* W4 */ plt_print("W4: esn \t%" PRIx64 " \t OR frag1_wqe_ptr \t0x%" PRIx64, - cpth->esn, cpth->frag1_wqe_ptr); + cpth->esn, plt_be_to_cpu_64(cpth->frag1_wqe_ptr)); + + /* offset of 0 implies 256B, otherwise it implies offset*8B */ + offset = cpth->w2.fi_offset; + offset = (((offset - 1) & 0x1f) + 1) * 8; + frag_info = PLT_PTR_ADD(cpth, offset); + + plt_print("CPT Fraginfo \t0x%p:", frag_info); + + /* W0 */ + plt_print("W0: f0.info \t0x%x", frag_info->w0.f0.info); + plt_print("W0: f1.info \t0x%x", frag_info->w0.f1.info); + plt_print("W0: f2.info \t0x%x", frag_info->w0.f2.info); + plt_print("W0: f3.info \t0x%x", frag_info->w0.f3.info); + + /* W1 */ + plt_print("W1: frag_size0 \t0x%x", frag_info->w1.frag_size0); + plt_print("W1: frag_size1 \t0x%x", frag_info->w1.frag_size1); + plt_print("W1: frag_size2 \t0x%x", frag_info->w1.frag_size2); + plt_print("W1: frag_size3 \t0x%x", frag_info->w1.frag_size3); + + slot = (uint64_t *)(frag_info + 1); + plt_print("Frag Slot2: WQE ptr \t%p", + (void *)plt_be_to_cpu_64(slot[0])); + plt_print("Frag Slot3: WQE ptr \t%p", + (void *)plt_be_to_cpu_64(slot[1])); } static int -- 2.8.4