From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 89ACBA0093; Fri, 17 Jun 2022 09:36:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AE4A74281C; Fri, 17 Jun 2022 09:36:19 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9400842905 for ; Fri, 17 Jun 2022 09:36:16 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25H3kwvC022796 for ; Fri, 17 Jun 2022 00:36:16 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ZXOnC/RUQf3VW+XAI8PhTHD5xBY6XiKintcEPTeq0oM=; b=WJn/eJiw9THxS4ybYgrlkLiK7E4MmrI8IT5Y/EireCKut8cqDYBZU31kJrDaSjZ07at+ JaUsp8rvH2rkRAFu7H3HBwlw/emICEzWBauG8Z/qYc1E0qxU30anzojXnhYOwVPS7j67 BuQZEgbAVVw0pdcLIGlM85KS09U/bICs5z0W+AomwUMPmJwO5HCrtc/EAIx4Jb/ddcOB 0LIHKFTiJyGbmNlH9sfSgTzb+qQlIwM4VAODveXFb0E/kj80CQbcT/WJA9X7R+ZW7aRO 6bqjgHR0NVtTr4Xx5CwPwZytDxl3bTr/kcih6VRVE7bfi4omPX6fT82fjR/VBEDviUpa hQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3grj05rrrb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 17 Jun 2022 00:36:15 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 17 Jun 2022 00:36:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 17 Jun 2022 00:36:13 -0700 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 3D85B3F7051; Fri, 17 Jun 2022 00:36:12 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Ankur Dwivedi , Subject: [PATCH 3/4] crypto/cnxk: support scatter gather mode Date: Fri, 17 Jun 2022 13:06:03 +0530 Message-ID: <20220617073604.889403-4-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220617073604.889403-1-ktejasree@marvell.com> References: <20220617073604.889403-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: suW-4_9OiLAYv5BRFPjq3CGK7s5DK30y X-Proofpoint-ORIG-GUID: suW-4_9OiLAYv5BRFPjq3CGK7s5DK30y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-17_06,2022-06-16_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding scatter gather support for zuc, snow3g and aes-ctr-cmac chained operations on cn9k. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cnxk_se.h | 149 +++++++++++++++++++++++++++++----- 1 file changed, 128 insertions(+), 21 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index 7429d66314..a2a97aa88f 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -1027,12 +1027,6 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, void *dm_vaddr; uint8_t *iv_d; - if (unlikely((!(req_flags & ROC_SE_SINGLE_BUF_INPLACE)) || - (!(req_flags & ROC_SE_SINGLE_BUF_HEADROOM)))) { - plt_dp_err("Scatter gather mode is not supported"); - return -1; - } - encr_offset = ROC_SE_ENCR_OFFSET(d_offs); auth_offset = ROC_SE_AUTH_OFFSET(d_offs); @@ -1084,28 +1078,141 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, else inputlen = encr_offset + encr_data_len; - dm_vaddr = params->bufs[0].vaddr; + if (likely(((req_flags & ROC_SE_SINGLE_BUF_INPLACE)) && + ((req_flags & ROC_SE_SINGLE_BUF_HEADROOM)))) { + + dm_vaddr = params->bufs[0].vaddr; - /* Use Direct mode */ + /* Use Direct mode */ + + offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr - + ROC_SE_OFF_CTRL_LEN - iv_len); - offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr - ROC_SE_OFF_CTRL_LEN - - iv_len); + /* DPTR */ + inst->dptr = (uint64_t)offset_vaddr; + /* RPTR should just exclude offset control word */ + inst->rptr = (uint64_t)dm_vaddr - iv_len; - /* DPTR */ - inst->dptr = (uint64_t)offset_vaddr; - /* RPTR should just exclude offset control word */ - inst->rptr = (uint64_t)dm_vaddr - iv_len; + cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN; - cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN; + *(uint64_t *)offset_vaddr = + rte_cpu_to_be_64(((uint64_t)(iv_offset) << 16) | + ((uint64_t)(encr_offset))); - *(uint64_t *)offset_vaddr = rte_cpu_to_be_64( - ((uint64_t)(iv_offset) << 16) | ((uint64_t)(encr_offset))); + iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); + pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv); + + iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16); + pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv); + + } else { + + struct roc_se_sglist_comp *scatter_comp, *gather_comp; + void *m_vaddr = params->meta_buf.vaddr; + uint32_t i, g_size_bytes, s_size_bytes; + uint8_t *in_buffer; + uint32_t size; + + /* save space for IV */ + offset_vaddr = m_vaddr; + + m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + + RTE_ALIGN_CEIL(iv_len, 8); + + cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE; + + /* DPTR has SG list */ + in_buffer = m_vaddr; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + gather_comp = + (struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8); + + /* Input Gather List */ + i = 0; + + /* Offset control word followed by iv */ + + i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr, + ROC_SE_OFF_CTRL_LEN + iv_len); + + *(uint64_t *)offset_vaddr = + rte_cpu_to_be_64(((uint64_t)(iv_offset) << 16) | + ((uint64_t)(encr_offset))); + + iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); + pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv); + + iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16); + pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv); + + /* input data */ + size = inputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, 0, &size, + NULL, 0); + if (unlikely(size)) { + plt_dp_err("Insufficient buffer space," + " size %d needed", + size); + return -1; + } + } + ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + g_size_bytes = + ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp); + + /* + * Output Scatter List + */ - iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); - pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv); + i = 0; + scatter_comp = + (struct roc_se_sglist_comp *)((uint8_t *)gather_comp + + g_size_bytes); + + if (iv_len) { + i = fill_sg_comp(scatter_comp, i, + (uint64_t)offset_vaddr + + ROC_SE_OFF_CTRL_LEN, + iv_len); + } - iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16); - pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv); + /* Add output data */ + if (se_ctx->ciph_then_auth && + (req_flags & ROC_SE_VALID_MAC_BUF)) + size = inputlen - iv_len; + else + /* Output including mac */ + size = inputlen - iv_len + mac_len; + + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, &size, + NULL, 0); + + if (unlikely(size)) { + plt_dp_err("Insufficient buffer space," + " size %d needed", + size); + return -1; + } + } + + ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + s_size_bytes = + ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp); + + size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE; + + /* This is DPTR len in case of SG mode */ + cpt_inst_w4.s.dlen = size; + + inst->dptr = (uint64_t)in_buffer; + } inst->w4.u64 = cpt_inst_w4.u64; -- 2.25.1