From: Jiawen Wu <jiawenwu@trustnetic.com>
To: dev@dpdk.org
Cc: Jiawen Wu <jiawenwu@trustnetic.com>, stable@dpdk.org
Subject: [PATCH 5/7] net/ngbe: fix YT PHY UTP mode to link up
Date: Mon, 20 Jun 2022 15:55:10 +0800 [thread overview]
Message-ID: <20220620075512.588744-6-jiawenwu@trustnetic.com> (raw)
In-Reply-To: <20220620075512.588744-1-jiawenwu@trustnetic.com>
Fix to read and write the correct register fields for yt8521s and
yt8531s PHY, since mode check was added.
Fixes: 1c44384fce76 ("net/ngbe: support custom PHY interfaces")
Cc: stable@dpdk.org
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
drivers/net/ngbe/base/ngbe_phy_yt.c | 42 ++++++++++++++---------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c
index f46121b8d1..9dd2b2264f 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.c
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.c
@@ -146,21 +146,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
}
/* duplex full */
value |= YT_BCR_DUPLEX | YT_BCR_RESET;
- hw->phy.write_reg(hw, YT_BCR, 0, value);
+ ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
goto skip_an;
}
/*disable 100/10base-T Self-negotiation ability*/
- hw->phy.read_reg(hw, YT_ANA, 0, &value);
+ ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |
YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF);
- hw->phy.write_reg(hw, YT_ANA, 0, value);
+ ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
/*disable 1000base-T Self-negotiation ability*/
- hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+ ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF);
- hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+ ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
if (speed & NGBE_LINK_SPEED_1GB_FULL) {
hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
@@ -176,19 +176,19 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
}
/* enable 1000base-T Self-negotiation ability */
- hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+ ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
value |= value_r9;
- hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+ ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
/* enable 100/10base-T Self-negotiation ability */
- hw->phy.read_reg(hw, YT_ANA, 0, &value);
+ ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
value |= value_r4;
- hw->phy.write_reg(hw, YT_ANA, 0, value);
+ ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
/* software reset to make the above configuration take effect*/
- hw->phy.read_reg(hw, YT_BCR, 0, &value);
+ ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN;
- hw->phy.write_reg(hw, YT_BCR, 0, value);
+ ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
skip_an:
hw->phy.set_phy_power(hw, true);
} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) {
@@ -219,15 +219,15 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
} else {
/* utp up */
/*disable 100/10base-T Self-negotiation ability*/
- hw->phy.read_reg(hw, YT_ANA, 0, &value);
+ ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |
YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF);
- hw->phy.write_reg(hw, YT_ANA, 0, value);
+ ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
/*disable 1000base-T Self-negotiation ability*/
- hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+ ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF);
- hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+ ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
if (speed & NGBE_LINK_SPEED_1GB_FULL) {
hw->phy.autoneg_advertised |=
@@ -246,21 +246,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
}
/* enable 1000base-T Self-negotiation ability */
- hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+ ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
value |= value_r9;
- hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+ ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
/* enable 100/10base-T Self-negotiation ability */
- hw->phy.read_reg(hw, YT_ANA, 0, &value);
+ ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
value |= value_r4;
- hw->phy.write_reg(hw, YT_ANA, 0, value);
+ ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
/* software reset to make the above configuration
* take effect
*/
- hw->phy.read_reg(hw, YT_BCR, 0, &value);
+ ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
value |= YT_BCR_RESET;
- hw->phy.write_reg(hw, YT_BCR, 0, value);
+ ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
}
} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) {
hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
--
2.27.0
next prev parent reply other threads:[~2022-06-20 7:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-20 7:55 [PATCH 0/7] Fixes and supports for Wangxun NICs Jiawen Wu
2022-06-20 7:55 ` [PATCH 1/7] net/txgbe: support OEM subsystem vendor ID Jiawen Wu
2022-06-21 12:19 ` Ferruh Yigit
2022-06-20 7:55 ` [PATCH 2/7] net/ngbe: " Jiawen Wu
2022-06-21 12:19 ` Ferruh Yigit
2022-06-20 7:55 ` [PATCH 3/7] net/txgbe: fix register polling Jiawen Wu
2022-06-21 12:19 ` Ferruh Yigit
2022-06-22 2:44 ` Jiawen Wu
2022-06-20 7:55 ` [PATCH 4/7] net/ngbe: add more packet statistics Jiawen Wu
2022-06-20 7:55 ` Jiawen Wu [this message]
2022-06-20 7:55 ` [PATCH 6/7] net/ngbe: support autoneg on/off for external PHY SFI mode Jiawen Wu
2022-06-20 7:55 ` [PATCH 7/7] net/ngbe: support YT PHY SGMII to RGMII mode Jiawen Wu
2022-06-21 12:20 ` [PATCH 0/7] Fixes and supports for Wangxun NICs Ferruh Yigit
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