[PATCH v2 0/7] Fixes and supports for Wangxun NICs

[PATCH v2 0/7] Fixes and supports for Wangxun NICs

[Jiawen Wu]

Fix the remaining bugs, support more OEM devices.

v2:
- remove useless variable initializers
- define macros for loop counts
- supplement detailed commit log

Jiawen Wu (7):
  net/txgbe: support OEM subsystem vendor ID
  net/ngbe: support OEM subsystem vendor ID
  net/txgbe: fix register polling
  net/ngbe: add more packet statistics
  net/ngbe: fix YT PHY UTP mode to link up
  net/ngbe: support autoneg on/off for external PHY SFI mode
  net/ngbe: support YT PHY SGMII to RGMII mode

 doc/guides/rel_notes/release_22_07.rst |   7 ++
 drivers/net/ngbe/base/ngbe_hw.c        |  13 +--
 drivers/net/ngbe/base/ngbe_phy_mvl.c   |  16 +++-
 drivers/net/ngbe/base/ngbe_phy_yt.c    | 111 ++++++++++++++++++++-----
 drivers/net/ngbe/base/ngbe_phy_yt.h    |   5 ++
 drivers/net/ngbe/base/ngbe_type.h      |   2 +-
 drivers/net/ngbe/ngbe_ethdev.c         |  22 ++++-
 drivers/net/txgbe/base/txgbe_hw.c      |  39 +++++++++
 drivers/net/txgbe/base/txgbe_hw.h      |   2 +
 drivers/net/txgbe/base/txgbe_regs.h    |  11 ++-
 drivers/net/txgbe/base/txgbe_type.h    |   1 +
 drivers/net/txgbe/txgbe_ethdev.c       |  13 +++
 12 files changed, 206 insertions(+), 36 deletions(-)

-- 
2.27.0

[PATCH v2 1/7] net/txgbe: support OEM subsystem vendor ID

[Jiawen Wu]

Add support for OEM subsystem vendor ID.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 doc/guides/rel_notes/release_22_07.rst |  4 +++
 drivers/net/txgbe/base/txgbe_hw.c      | 39 ++++++++++++++++++++++++++
 drivers/net/txgbe/base/txgbe_hw.h      |  2 ++
 drivers/net/txgbe/base/txgbe_type.h    |  1 +
 drivers/net/txgbe/txgbe_ethdev.c       | 13 +++++++++
 5 files changed, 59 insertions(+)

diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index 6fc044edaa..96db85a707 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -167,6 +167,10 @@ New Features
 
   * Added support for yt8531s PHY.
 
+* **Updated Wangxun txgbe driver.**
+
+  * Added support for OEM subsystem vendor ID.
+
 * **Added Elliptic Curve Diffie-Hellman (ECDH) algorithm in cryptodev.**
 
   Added support for Elliptic Curve Diffie Hellman (ECDH) asymmetric
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 6a045cba79..8966453a03 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -2608,6 +2608,45 @@ s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 autoc)
 	return err;
 }
 
+/* cmd_addr is used for some special command:
+ * 1. to be sector address, when implemented erase sector command
+ * 2. to be flash address when implemented read, write flash address
+ *
+ * Return 0 on success, return 1 on failure.
+ */
+u32 txgbe_fmgr_cmd_op(struct txgbe_hw *hw, u32 cmd, u32 cmd_addr)
+{
+	u32 cmd_val, i;
+
+	cmd_val = TXGBE_SPICMD_CMD(cmd) | TXGBE_SPICMD_CLK(3) | cmd_addr;
+	wr32(hw, TXGBE_SPICMD, cmd_val);
+
+	for (i = 0; i < TXGBE_SPI_TIMEOUT; i++) {
+		if (rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_OPDONE)
+			break;
+
+		usec_delay(10);
+	}
+
+	if (i == TXGBE_SPI_TIMEOUT)
+		return 1;
+
+	return 0;
+}
+
+u32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr)
+{
+	u32 status;
+
+	status = txgbe_fmgr_cmd_op(hw, 1, addr);
+	if (status == 0x1) {
+		DEBUGOUT("Read flash timeout.");
+		return status;
+	}
+
+	return rd32(hw, TXGBE_SPIDAT);
+}
+
 /**
  *  txgbe_init_ops_pf - Inits func ptrs and MAC type
  *  @hw: pointer to hardware structure
diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h
index fd2f7d784c..7031589f7c 100644
--- a/drivers/net/txgbe/base/txgbe_hw.h
+++ b/drivers/net/txgbe/base/txgbe_hw.h
@@ -111,4 +111,6 @@ s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value);
 s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 value);
 s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw);
 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw);
+u32 txgbe_fmgr_cmd_op(struct txgbe_hw *hw, u32 cmd, u32 cmd_addr);
+u32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr);
 #endif /* _TXGBE_HW_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index d95467f9f8..343279127f 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -28,6 +28,7 @@
 #define TXGBE_FDIR_INIT_DONE_POLL		10
 #define TXGBE_FDIRCMD_CMD_POLL			10
 #define TXGBE_VF_INIT_TIMEOUT	200 /* Number of retries to clear RSTI */
+#define TXGBE_SPI_TIMEOUT	10000
 
 #define TXGBE_ALIGN		128 /* as intel did */
 
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index f0994f028d..dc8c3c70a9 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -594,6 +594,19 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 	/* Vendor and Device ID need to be set before init of shared code */
 	hw->device_id = pci_dev->id.device_id;
 	hw->vendor_id = pci_dev->id.vendor_id;
+	if (pci_dev->id.subsystem_vendor_id == PCI_VENDOR_ID_WANGXUN) {
+		hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
+	} else {
+		u32 ssid;
+
+		ssid = txgbe_flash_read_dword(hw, 0xFFFDC);
+		if (ssid == 0x1) {
+			PMD_INIT_LOG(ERR,
+				"Read of internal subsystem device id failed\n");
+			return -ENODEV;
+		}
+		hw->subsystem_device_id = (u16)ssid >> 8 | (u16)ssid << 8;
+	}
 	hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 	hw->allow_unsupported_sfp = 1;
 
-- 
2.27.0

[PATCH v2 2/7] net/ngbe: support OEM subsystem vendor ID

[Jiawen Wu]

Add support for OEM subsystem vendor ID.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 doc/guides/rel_notes/release_22_07.rst |  1 +
 drivers/net/ngbe/base/ngbe_hw.c        | 13 +++++++------
 drivers/net/ngbe/base/ngbe_type.h      |  2 +-
 drivers/net/ngbe/ngbe_ethdev.c         | 14 +++++++++++++-
 4 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index 96db85a707..b26efb8719 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -166,6 +166,7 @@ New Features
 * **Updated Wangxun ngbe driver.**
 
   * Added support for yt8531s PHY.
+  * Added support for OEM subsystem vendor ID.
 
 * **Updated Wangxun txgbe driver.**
 
diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c
index c1114ba3b1..283cdca367 100644
--- a/drivers/net/ngbe/base/ngbe_hw.c
+++ b/drivers/net/ngbe/base/ngbe_hw.c
@@ -1822,22 +1822,23 @@ s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
 /* cmd_addr is used for some special command:
  * 1. to be sector address, when implemented erase sector command
  * 2. to be flash address when implemented read, write flash address
+ *
+ * Return 0 on success, return 1 on failure.
  */
 u32 ngbe_fmgr_cmd_op(struct ngbe_hw *hw, u32 cmd, u32 cmd_addr)
 {
-	u32 cmd_val = 0;
-	u32 i = 0;
+	u32 cmd_val, i;
 
 	cmd_val = NGBE_SPICMD_CMD(cmd) | NGBE_SPICMD_CLK(3) | cmd_addr;
 	wr32(hw, NGBE_SPICMD, cmd_val);
 
-	for (i = 0; i < 10000; i++) {
+	for (i = 0; i < NGBE_SPI_TIMEOUT; i++) {
 		if (rd32(hw, NGBE_SPISTAT) & NGBE_SPISTAT_OPDONE)
 			break;
 
 		usec_delay(10);
 	}
-	if (i == 10000)
+	if (i == NGBE_SPI_TIMEOUT)
 		return 1;
 
 	return 0;
@@ -1845,10 +1846,10 @@ u32 ngbe_fmgr_cmd_op(struct ngbe_hw *hw, u32 cmd, u32 cmd_addr)
 
 u32 ngbe_flash_read_dword(struct ngbe_hw *hw, u32 addr)
 {
-	u32 status = 0;
+	u32 status;
 
 	status = ngbe_fmgr_cmd_op(hw, 1, addr);
-	if (status) {
+	if (status == 0x1) {
 		DEBUGOUT("Read flash timeout.");
 		return status;
 	}
diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h
index 0ad4766d2a..4a6c273f1e 100644
--- a/drivers/net/ngbe/base/ngbe_type.h
+++ b/drivers/net/ngbe/base/ngbe_type.h
@@ -18,7 +18,7 @@
 #define NGBE_MAX_UTA              128
 
 #define NGBE_PCI_MASTER_DISABLE_TIMEOUT	800
-
+#define NGBE_SPI_TIMEOUT	10000
 
 #define NGBE_ALIGN		128 /* as intel did */
 #define NGBE_ISB_SIZE		16
diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c
index 5ac1c27a58..ee09d54c2f 100644
--- a/drivers/net/ngbe/ngbe_ethdev.c
+++ b/drivers/net/ngbe/ngbe_ethdev.c
@@ -359,7 +359,19 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 	hw->back = pci_dev;
 	hw->device_id = pci_dev->id.device_id;
 	hw->vendor_id = pci_dev->id.vendor_id;
-	hw->sub_system_id = pci_dev->id.subsystem_device_id;
+	if (pci_dev->id.subsystem_vendor_id == PCI_VENDOR_ID_WANGXUN) {
+		hw->sub_system_id = pci_dev->id.subsystem_device_id;
+	} else {
+		u32 ssid;
+
+		ssid = ngbe_flash_read_dword(hw, 0xFFFDC);
+		if (ssid == 0x1) {
+			PMD_INIT_LOG(ERR,
+				"Read of internal subsystem device id failed\n");
+			return -ENODEV;
+		}
+		hw->sub_system_id = (u16)ssid >> 8 | (u16)ssid << 8;
+	}
 	ngbe_map_device_id(hw);
 	hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 
-- 
2.27.0

[PATCH v2 3/7] net/txgbe: fix register polling

[Jiawen Wu]

Fix to poll some specific registers, which expect bit value 0.

'w32w' is used in registers where the write command bit is set and
waits for the bit clear to complete the write.

Fixes: 24a4c76aff4d ("net/txgbe: add error types and registers")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/txgbe/base/txgbe_regs.h | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index 3139796911..911bb6e04e 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -1864,8 +1864,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,
 	}
 
 	do {
-		all |= rd32(hw, reg);
-		value |= mask & all;
+		if (expect != 0) {
+			all |= rd32(hw, reg);
+			value |= mask & all;
+		} else {
+			all = rd32(hw, reg);
+			value = mask & all;
+		}
 		if (value == expect)
 			break;
 
@@ -1898,7 +1903,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,
 
 #define wr32w(hw, reg, val, mask, slice) do { \
 	wr32((hw), reg, val); \
-	po32m((hw), reg, mask, mask, NULL, 5, slice); \
+	po32m((hw), reg, mask, 0, NULL, 5, slice); \
 } while (0)
 
 #define TXGBE_XPCS_IDAADDR    0x13000
-- 
2.27.0

[PATCH v2 4/7] net/ngbe: add more packet statistics

[Jiawen Wu]

Add more hardware extended statistics.

Fixes: 8b433d04adc9 ("net/ngbe: support device xstats")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/ngbe/ngbe_ethdev.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c
index ee09d54c2f..308c231183 100644
--- a/drivers/net/ngbe/ngbe_ethdev.c
+++ b/drivers/net/ngbe/ngbe_ethdev.c
@@ -164,6 +164,8 @@ static const struct rte_ngbe_xstats_name_off rte_ngbe_stats_strings[] = {
 	HW_XSTAT(rx_management_packets),
 	HW_XSTAT(tx_management_packets),
 	HW_XSTAT(rx_management_dropped),
+	HW_XSTAT(rx_dma_drop),
+	HW_XSTAT(tx_secdrp_packets),
 
 	/* Basic Error */
 	HW_XSTAT(rx_crc_errors),
@@ -179,6 +181,12 @@ static const struct rte_ngbe_xstats_name_off rte_ngbe_stats_strings[] = {
 	HW_XSTAT(mac_local_errors),
 	HW_XSTAT(mac_remote_errors),
 
+	/* PB Stats */
+	HW_XSTAT(rx_up_dropped),
+	HW_XSTAT(rdb_pkt_cnt),
+	HW_XSTAT(rdb_repli_cnt),
+	HW_XSTAT(rdb_drp_cnt),
+
 	/* MACSEC */
 	HW_XSTAT(tx_macsec_pkts_untagged),
 	HW_XSTAT(tx_macsec_pkts_encrypted),
-- 
2.27.0

[PATCH v2 5/7] net/ngbe: fix YT PHY UTP mode to link up

[Jiawen Wu]

Fix to read and write the correct register fields for yt8521s and
yt8531s PHY, since mode check was added.

Fixes: 1c44384fce76 ("net/ngbe: support custom PHY interfaces")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/ngbe/base/ngbe_phy_yt.c | 42 ++++++++++++++---------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c
index f46121b8d1..9dd2b2264f 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.c
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.c
@@ -146,21 +146,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 			}
 			/* duplex full */
 			value |= YT_BCR_DUPLEX | YT_BCR_RESET;
-			hw->phy.write_reg(hw, YT_BCR, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
 
 			goto skip_an;
 		}
 
 		/*disable 100/10base-T Self-negotiation ability*/
-		hw->phy.read_reg(hw, YT_ANA, 0, &value);
+		ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
 		value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |
 			YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF);
-		hw->phy.write_reg(hw, YT_ANA, 0, value);
+		ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
 
 		/*disable 1000base-T Self-negotiation ability*/
-		hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+		ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
 		value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF);
-		hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+		ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
 
 		if (speed & NGBE_LINK_SPEED_1GB_FULL) {
 			hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
@@ -176,19 +176,19 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 		}
 
 		/* enable 1000base-T Self-negotiation ability */
-		hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+		ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
 		value |= value_r9;
-		hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+		ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
 
 		/* enable 100/10base-T Self-negotiation ability */
-		hw->phy.read_reg(hw, YT_ANA, 0, &value);
+		ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
 		value |= value_r4;
-		hw->phy.write_reg(hw, YT_ANA, 0, value);
+		ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
 
 		/* software reset to make the above configuration take effect*/
-		hw->phy.read_reg(hw, YT_BCR, 0, &value);
+		ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
 		value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN;
-		hw->phy.write_reg(hw, YT_BCR, 0, value);
+		ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
 skip_an:
 		hw->phy.set_phy_power(hw, true);
 	} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) {
@@ -219,15 +219,15 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 		} else {
 			/* utp up */
 			/*disable 100/10base-T Self-negotiation ability*/
-			hw->phy.read_reg(hw, YT_ANA, 0, &value);
+			ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
 			value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |
 				YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF);
-			hw->phy.write_reg(hw, YT_ANA, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
 
 			/*disable 1000base-T Self-negotiation ability*/
-			hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+			ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
 			value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF);
-			hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
 
 			if (speed & NGBE_LINK_SPEED_1GB_FULL) {
 				hw->phy.autoneg_advertised |=
@@ -246,21 +246,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 			}
 
 			/* enable 1000base-T Self-negotiation ability */
-			hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+			ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
 			value |= value_r9;
-			hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
 
 			/* enable 100/10base-T Self-negotiation ability */
-			hw->phy.read_reg(hw, YT_ANA, 0, &value);
+			ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
 			value |= value_r4;
-			hw->phy.write_reg(hw, YT_ANA, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
 
 			/* software reset to make the above configuration
 			 * take effect
 			 */
-			hw->phy.read_reg(hw, YT_BCR, 0, &value);
+			ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
 			value |= YT_BCR_RESET;
-			hw->phy.write_reg(hw, YT_BCR, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
 		}
 	} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) {
 		hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
-- 
2.27.0

[PATCH v2 6/7] net/ngbe: support autoneg on/off for external PHY SFI mode

[Jiawen Wu]

Add support for external PHY to switch autoneg on/off on their SFI mode.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 doc/guides/rel_notes/release_22_07.rst |  1 +
 drivers/net/ngbe/base/ngbe_phy_mvl.c   | 16 +++++++++++++---
 drivers/net/ngbe/base/ngbe_phy_yt.c    | 20 +++++++++++++++++++-
 drivers/net/ngbe/base/ngbe_phy_yt.h    |  5 +++++
 4 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index b26efb8719..a84c5b486b 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -167,6 +167,7 @@ New Features
 
   * Added support for yt8531s PHY.
   * Added support for OEM subsystem vendor ID.
+  * Added autoneg on/off for external PHY SFI mode.
 
 * **Updated Wangxun txgbe driver.**
 
diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.c b/drivers/net/ngbe/base/ngbe_phy_mvl.c
index c5256359ed..8746a72eb3 100644
--- a/drivers/net/ngbe/base/ngbe_phy_mvl.c
+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.c
@@ -203,6 +203,10 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
 			   MVL_PHY_1000BASET_HALF);
 		value_r9 |= value;
 		hw->phy.write_reg(hw, MVL_PHY_1000BASET, 0, value_r9);
+
+		value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE |
+			MVL_CTRL_RESET | MVL_CTRL_DUPLEX;
+		ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
 	} else {
 		hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
 
@@ -210,10 +214,16 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
 		value &= ~(MVL_PHY_1000BASEX_HALF | MVL_PHY_1000BASEX_FULL);
 		value |= MVL_PHY_1000BASEX_FULL;
 		hw->phy.write_reg(hw, MVL_ANA, 0, value);
-	}
 
-	value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | MVL_CTRL_RESET;
-	ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
+		if (hw->mac.autoneg)
+			value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE |
+				MVL_CTRL_RESET | MVL_CTRL_DUPLEX |
+				MVL_CTRL_SPEED_SELECT1;
+		else
+			value = MVL_CTRL_RESET | MVL_CTRL_DUPLEX |
+				MVL_CTRL_SPEED_SELECT1;
+		ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
+	}
 
 skip_an:
 	hw->phy.set_phy_power(hw, true);
diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c
index 9dd2b2264f..bc1921e68a 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.c
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.c
@@ -205,8 +205,26 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 			YT_CHIP_SW_RST;
 		ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
 
+		ngbe_read_phy_reg_sds_ext_yt(hw, YT_AUTO, 0, &value);
+		value &= ~YT_AUTO_SENSING;
+		ngbe_write_phy_reg_sds_ext_yt(hw, YT_AUTO, 0, value);
+
+		ngbe_read_phy_reg_ext_yt(hw, YT_MISC, 0, &value);
+		value |= YT_MISC_RESV;
+		ngbe_write_phy_reg_ext_yt(hw, YT_MISC, 0, value);
+
+		ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);
+		value &= ~YT_CHIP_SW_RST;
+		ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
+
 		/* software reset */
-		ngbe_write_phy_reg_sds_ext_yt(hw, 0x0, 0, 0x9140);
+		if (hw->mac.autoneg)
+			value = YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN |
+				YT_BCR_DUPLEX | YT_BCR_SPEED_SELECT1;
+		else
+			value = YT_BCR_RESET | YT_BCR_DUPLEX |
+				YT_BCR_SPEED_SELECT1;
+		hw->phy.write_reg(hw, YT_BCR, 0, value);
 
 		hw->phy.set_phy_power(hw, true);
 	} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) {
diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.h b/drivers/net/ngbe/base/ngbe_phy_yt.h
index 06e8f77261..ddf992e79a 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.h
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.h
@@ -31,6 +31,11 @@
 #define   YT_RGMII_CONF2_LINKUP		MS16(4, 0x1)
 #define YT_MISC				0xA006
 #define   YT_MISC_FIBER_PRIO		MS16(8, 0x1) /* 0 for UTP */
+#define   YT_MISC_RESV			MS16(0, 0x1)
+
+/* SDS EXT */
+#define YT_AUTO				0xA5
+#define   YT_AUTO_SENSING		MS16(15, 0x1)
 
 /* MII common registers in UTP and SDS */
 #define YT_BCR				0x0
-- 
2.27.0

[PATCH v2 7/7] net/ngbe: support YT PHY SGMII to RGMII mode

[Jiawen Wu]

Add SGMII to RGMII mode for yt8521s and yt8531s PHY.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 doc/guides/rel_notes/release_22_07.rst |  1 +
 drivers/net/ngbe/base/ngbe_phy_yt.c    | 49 ++++++++++++++++++++++++++
 2 files changed, 50 insertions(+)

diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index a84c5b486b..6baa63e3bf 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -168,6 +168,7 @@ New Features
   * Added support for yt8531s PHY.
   * Added support for OEM subsystem vendor ID.
   * Added autoneg on/off for external PHY SFI mode.
+  * Added support for yt8521s/yt8531s PHY SGMII to RGMII mode.
 
 * **Updated Wangxun txgbe driver.**
 
diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c
index bc1921e68a..562a0dede5 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.c
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.c
@@ -298,6 +298,55 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 		value &= ~YT_SMI_PHY_SW_RST;
 		ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
 
+		hw->phy.set_phy_power(hw, true);
+	} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(5)) {
+		/* sgmii_to_rgmii */
+		if (!hw->mac.autoneg) {
+			switch (speed) {
+			case NGBE_LINK_SPEED_1GB_FULL:
+				value = YT_BCR_SPEED_SELECT1;
+				break;
+			case NGBE_LINK_SPEED_100M_FULL:
+				value = YT_BCR_SPEED_SELECT0;
+				break;
+			case NGBE_LINK_SPEED_10M_FULL:
+				value = 0;
+				break;
+			default:
+				value = YT_BCR_SPEED_SELECT0 |
+					YT_BCR_SPEED_SELECT1;
+				DEBUGOUT("unknown speed = 0x%x", speed);
+				break;
+			}
+			/* duplex full */
+			value |= YT_BCR_DUPLEX | YT_BCR_RESET;
+			hw->phy.write_reg(hw, YT_BCR, 0, value);
+
+			goto skip_an_sr;
+		}
+
+		value = 0;
+		if (speed & NGBE_LINK_SPEED_1GB_FULL) {
+			hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
+			value |= YT_BCR_SPEED_SELECT1;
+		}
+		if (speed & NGBE_LINK_SPEED_100M_FULL) {
+			hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_100M_FULL;
+			value |= YT_BCR_SPEED_SELECT0;
+		}
+		if (speed & NGBE_LINK_SPEED_10M_FULL)
+			hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_10M_FULL;
+
+		/* duplex full */
+		value |= YT_BCR_DUPLEX | YT_BCR_RESET;
+		hw->phy.write_reg(hw, YT_BCR, 0, value);
+
+		/* software reset to make the above configuration take effect */
+		hw->phy.read_reg(hw, YT_BCR, 0, &value);
+		value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN;
+		hw->phy.write_reg(hw, 0x0, 0, value);
+
+skip_an_sr:
 		hw->phy.set_phy_power(hw, true);
 	}
 
-- 
2.27.0

Re: [PATCH v2 0/7] Fixes and supports for Wangxun NICs

[Ferruh Yigit]

On 6/22/2022 7:56 AM, Jiawen Wu wrote:
> Fix the remaining bugs, support more OEM devices.
> 
> v2:
> - remove useless variable initializers
> - define macros for loop counts
> - supplement detailed commit log
> 
> Jiawen Wu (7):
>    net/txgbe: support OEM subsystem vendor ID
>    net/ngbe: support OEM subsystem vendor ID
>    net/txgbe: fix register polling
>    net/ngbe: add more packet statistics
>    net/ngbe: fix YT PHY UTP mode to link up
>    net/ngbe: support autoneg on/off for external PHY SFI mode
>    net/ngbe: support YT PHY SGMII to RGMII mode
> 

Series applied to dpdk-next-net/main, thanks.


Please send new version of the sets as reply to previous version to keep 
them all in same email thread.

RE: [PATCH v2 0/7] Fixes and supports for Wangxun NICs

[Jiawen Wu]

On Wednesday, June 22, 2022 6:56 PM, Ferruh Yigit wrote:
> On 6/22/2022 7:56 AM, Jiawen Wu wrote:
> > Fix the remaining bugs, support more OEM devices.
> >
> > v2:
> > - remove useless variable initializers
> > - define macros for loop counts
> > - supplement detailed commit log
> >
> > Jiawen Wu (7):
> >    net/txgbe: support OEM subsystem vendor ID
> >    net/ngbe: support OEM subsystem vendor ID
> >    net/txgbe: fix register polling
> >    net/ngbe: add more packet statistics
> >    net/ngbe: fix YT PHY UTP mode to link up
> >    net/ngbe: support autoneg on/off for external PHY SFI mode
> >    net/ngbe: support YT PHY SGMII to RGMII mode
> >
> 
> Series applied to dpdk-next-net/main, thanks.
> 
> 
> Please send new version of the sets as reply to previous version to keep them
> all in same email thread.

Okay, get it.