[PATCH v2 6/7] net/ngbe: support autoneg on/off for external PHY SFI mode

[Jiawen Wu <jiawenwu@trustnetic.com>]

Add support for external PHY to switch autoneg on/off on their SFI mode.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 doc/guides/rel_notes/release_22_07.rst |  1 +
 drivers/net/ngbe/base/ngbe_phy_mvl.c   | 16 +++++++++++++---
 drivers/net/ngbe/base/ngbe_phy_yt.c    | 20 +++++++++++++++++++-
 drivers/net/ngbe/base/ngbe_phy_yt.h    |  5 +++++
 4 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index b26efb8719..a84c5b486b 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -167,6 +167,7 @@ New Features
 
   * Added support for yt8531s PHY.
   * Added support for OEM subsystem vendor ID.
+  * Added autoneg on/off for external PHY SFI mode.
 
 * **Updated Wangxun txgbe driver.**
 
diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.c b/drivers/net/ngbe/base/ngbe_phy_mvl.c
index c5256359ed..8746a72eb3 100644
--- a/drivers/net/ngbe/base/ngbe_phy_mvl.c
+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.c
@@ -203,6 +203,10 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
 			   MVL_PHY_1000BASET_HALF);
 		value_r9 |= value;
 		hw->phy.write_reg(hw, MVL_PHY_1000BASET, 0, value_r9);
+
+		value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE |
+			MVL_CTRL_RESET | MVL_CTRL_DUPLEX;
+		ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
 	} else {
 		hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
 
@@ -210,10 +214,16 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
 		value &= ~(MVL_PHY_1000BASEX_HALF | MVL_PHY_1000BASEX_FULL);
 		value |= MVL_PHY_1000BASEX_FULL;
 		hw->phy.write_reg(hw, MVL_ANA, 0, value);
-	}
 
-	value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | MVL_CTRL_RESET;
-	ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
+		if (hw->mac.autoneg)
+			value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE |
+				MVL_CTRL_RESET | MVL_CTRL_DUPLEX |
+				MVL_CTRL_SPEED_SELECT1;
+		else
+			value = MVL_CTRL_RESET | MVL_CTRL_DUPLEX |
+				MVL_CTRL_SPEED_SELECT1;
+		ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
+	}
 
 skip_an:
 	hw->phy.set_phy_power(hw, true);
diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c
index 9dd2b2264f..bc1921e68a 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.c
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.c
@@ -205,8 +205,26 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 			YT_CHIP_SW_RST;
 		ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
 
+		ngbe_read_phy_reg_sds_ext_yt(hw, YT_AUTO, 0, &value);
+		value &= ~YT_AUTO_SENSING;
+		ngbe_write_phy_reg_sds_ext_yt(hw, YT_AUTO, 0, value);
+
+		ngbe_read_phy_reg_ext_yt(hw, YT_MISC, 0, &value);
+		value |= YT_MISC_RESV;
+		ngbe_write_phy_reg_ext_yt(hw, YT_MISC, 0, value);
+
+		ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);
+		value &= ~YT_CHIP_SW_RST;
+		ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
+
 		/* software reset */
-		ngbe_write_phy_reg_sds_ext_yt(hw, 0x0, 0, 0x9140);
+		if (hw->mac.autoneg)
+			value = YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN |
+				YT_BCR_DUPLEX | YT_BCR_SPEED_SELECT1;
+		else
+			value = YT_BCR_RESET | YT_BCR_DUPLEX |
+				YT_BCR_SPEED_SELECT1;
+		hw->phy.write_reg(hw, YT_BCR, 0, value);
 
 		hw->phy.set_phy_power(hw, true);
 	} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) {
diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.h b/drivers/net/ngbe/base/ngbe_phy_yt.h
index 06e8f77261..ddf992e79a 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.h
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.h
@@ -31,6 +31,11 @@
 #define   YT_RGMII_CONF2_LINKUP		MS16(4, 0x1)
 #define YT_MISC				0xA006
 #define   YT_MISC_FIBER_PRIO		MS16(8, 0x1) /* 0 for UTP */
+#define   YT_MISC_RESV			MS16(0, 0x1)
+
+/* SDS EXT */
+#define YT_AUTO				0xA5
+#define   YT_AUTO_SENSING		MS16(15, 0x1)
 
 /* MII common registers in UTP and SDS */
 #define YT_BCR				0x0
-- 
2.27.0