From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F0479A057D; Tue, 28 Jun 2022 16:59:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0FE96410F2; Tue, 28 Jun 2022 16:58:59 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2062.outbound.protection.outlook.com [40.107.223.62]) by mails.dpdk.org (Postfix) with ESMTP id 593A340A7A for ; Tue, 28 Jun 2022 16:58:54 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FyBLfgXDrACeK3CxcRJAKeY0BI2wWdnZoJS+3ikHxqBrAnZdAn0dzKn8HGCGdJS9Mpt8SSG1j67PqOG/RVDtB9A+pJt84fRMWp26AqLAL4UQlnvpggnitBCji+Ivsj/z76u6kuan2Kx24goccgsG+vmGB/xPevROYnEppyalOaMlyjFvEDIY79Gx93rQ3/Nyz8aNQZfhuP4XF1jvx4WStbPfPFQAZEgBwKxgC7pRrJJiKIRTeofOK6KknWsEW0dRr8PNjIQA6EslekrIIxrtUIVig6e7IQZ8XQjnzET9YCJ7bAKMrnfYLO9UjOcXjGo/R7KH+TCxCyR5TrgC2crJ/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+LP+kwqde0LhJMBsk2yycxIFd8h1EInvgqiz63DrUMU=; b=HeMhmQfjHNUDzkP6tq7ujXkJ/v6t5v0mvd7unqUrkXMFV+8vXHnn1SXggn/RnFRFjqzQWh+lWS2VpbmdWZ9MVqL3aEuxiq9hZthondR8wblxLZIzAyJCvCIOmDRKOu/Z1KNMEh9xViRyuY79EhpD14KvFPIucqy670eHOKsU8s36qfwUYpB2oHcqzYoDUmzM+IoGclJipxlmJtWcooXj20TLSIJiX5B8JyP3kGaf+vTEdsrzte/SMPf2U/+lxzMAdWKGb31EVdBgNeE+N+tD+TsLVwDOfLkr5Ah0AfsU9yJfWG+Jyf/GVAXMQj8pvm8KC8slQ44B1fOyzsHlq0wKMg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+LP+kwqde0LhJMBsk2yycxIFd8h1EInvgqiz63DrUMU=; b=eiemO909snN2Gw2ZH12xPHGGCS3EngGdgEw3fdZrCHeEpuLiwiplKVmZTH2Clf/Krc8jyLgYklXVgEqY9ox/NlZdCYx3vBGCE7ygHnpsew+z9CDqhLY8mSxqb0XHmfZN857PKqRXwVcjHirV0Jck8q8aTDN/rTtMaO+hbW6cI5JNA9eEDgx4ygEE+IFd/aPamo/IwICxBGrmt0IvuuKQ+yZttCHUHlEI58fpYWkoCjkA4mp3GuyCyDQ2VLljGIzUdJHpbJT5LjhX7VE6JxbANpuHB5TZpdumfjMr5Nw6au6llH/4xuBV5xvO/b7C+AbAupHi2z3+UBEpfim+ptWDLg== Received: from DM6PR12CA0007.namprd12.prod.outlook.com (2603:10b6:5:1c0::20) by BYAPR12MB3111.namprd12.prod.outlook.com (2603:10b6:a03:dd::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5373.15; Tue, 28 Jun 2022 14:58:52 +0000 Received: from DM6NAM11FT015.eop-nam11.prod.protection.outlook.com (2603:10b6:5:1c0:cafe::f0) by DM6PR12CA0007.outlook.office365.com (2603:10b6:5:1c0::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5395.14 via Frontend Transport; Tue, 28 Jun 2022 14:58:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by DM6NAM11FT015.mail.protection.outlook.com (10.13.172.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5373.15 via Frontend Transport; Tue, 28 Jun 2022 14:58:51 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 28 Jun 2022 14:58:51 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Tue, 28 Jun 2022 07:58:50 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26 via Frontend Transport; Tue, 28 Jun 2022 07:58:48 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Thomas Monjalon Subject: [PATCH v3 2/2] net/mlx5: add test for external Rx queue Date: Tue, 28 Jun 2022 17:58:41 +0300 Message-ID: <20220628145841.3364471-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220628145841.3364471-1-michaelba@nvidia.com> References: <20220616171017.2597941-1-michaelba@nvidia.com> <20220628145841.3364471-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b25c2ae5-5efc-4580-2079-08da5916b6d4 X-MS-TrafficTypeDiagnostic: BYAPR12MB3111:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HhGigl4OGGnNkGNWI5tAc+6EJQKlAPmzbg3PIljq1SI55Y8ZEj6wVhQ46sg5Cc9dQ53d/2K8Hun6b3/TZOcxcYztlRLgZaeuZPFnT7wVo4ReZGAwqkSegEJqE9i59+bFur+h/AlYlmYyRtdTMzbfcSmdzkRIFBkmriC8bUML9yJmDwobQoOF/FZ4qyRW+I6Vf7M6R7WmEMppx6Q3+4tRacqmA4GPzpIu4IQejeshF/W3R1Ik98snVEDkkMChFvxCp1EZsjMW05DzD07tNuPgKMQr+PaY2ADLFJsrxlBSkxR+dQaJ9eD/Dr6BbG60PtF1PPOuGUe5pTRdL6PNuA+ALDiMt2lNv9+IuRo+M/h/DfDr/NhJF/3KewKI8xuJ+daJ5h+FevksRP711xzpshYAONgPUwqd2ZBkBB7RmbR5hDHonlF62/wYo+ZmylJ1lJjtESc6y3b0OaKwdpfqsHJ5eA8WKYlkOPQATyO07fXZ0OEbZzoyqEofMSJahNNioZjc5BeCkCTpsUuIdnnH/3QjOwhIgOTNYjMh4jReDN0xCTHemKshyl8ryqYxAA7cjdwPUwvlLewvlXdiVEaIHBuvQVwjXwQMm6WXSI6AGQvmT2GajGxR8mVk8GNn4Ws8texacpyKrPAvrYZuIEt+vvYvXrPeCjPeFYNVE6UVCfbcEfjGpmXmexH6YYLPqhPgm6zjSmJ8ylkbA6EMM5l+CS+gqxSX4n2iyFWhcmiStCo0x3um6K0r15PKOkUFsBnCLNtZcdvy4INbjMIt1SZoRxlA1cLCjjJZeqLakYRdkbxXzA442Frt0PdO6iRVWsuIEjyYKaQNwdsZj+xJf4SCqI2M+g== X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(396003)(136003)(346002)(376002)(40470700004)(46966006)(36840700001)(40460700003)(82740400003)(316002)(8676002)(4326008)(81166007)(55016003)(6666004)(5660300002)(336012)(47076005)(426003)(478600001)(2616005)(1076003)(186003)(41300700001)(70206006)(7696005)(2906002)(356005)(70586007)(54906003)(8936002)(26005)(6916009)(36860700001)(36756003)(6286002)(40480700001)(86362001)(82310400005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2022 14:58:51.6760 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b25c2ae5-5efc-4580-2079-08da5916b6d4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3111 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add mlx5 internal test for map and unmap external RxQs. This patch adds to Testpmd app a runtime function to test the mapping API. For insert mapping use this command: testpmd> mlx5 port (port_id) ext_rxq map (sw_queue_id) (hw_queue_id) For insert mapping use this command: testpmd> mlx5 port (port_id) ext_rxq unmap (sw_queue_id) Signed-off-by: Michael Baum Reviewed-by: Thomas Monjalon Acked-by: Matan Azrad --- doc/guides/nics/mlx5.rst | 19 ++++ drivers/net/mlx5/mlx5_testpmd.c | 163 ++++++++++++++++++++++++++++++++ 2 files changed, 182 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index cd3a613640..9f2832e284 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1840,3 +1840,22 @@ and its socket path is ``/var/run/import_ipc_socket``: Port 0 is attached. Now total ports is 1 Done + +port map external Rx queue +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +External Rx queue indexes mapping management. + +Map HW queue index (32-bit) to ethdev queue index (16-bit) for external Rx queue:: + + testpmd> mlx5 port (port_id) ext_rxq map (sw_queue_id) (hw_queue_id) + +Unmap external Rx queue:: + + testpmd> mlx5 port (port_id) ext_rxq unmap (sw_queue_id) + +where: + +* ``sw_queue_id``: queue index in range [64536, 65535]. + This range is the highest 1000 numbers. +* ``hw_queue_id``: queue index given by HW in queue creation. diff --git a/drivers/net/mlx5/mlx5_testpmd.c b/drivers/net/mlx5/mlx5_testpmd.c index 463ee8e764..ed845834aa 100644 --- a/drivers/net/mlx5/mlx5_testpmd.c +++ b/drivers/net/mlx5/mlx5_testpmd.c @@ -401,6 +401,158 @@ static cmdline_parse_inst_t mlx5_cmd_operate_attach_port = { }; #endif +/* Map HW queue index to rte queue index. */ +struct mlx5_cmd_map_ext_rxq { + cmdline_fixed_string_t mlx5; + cmdline_fixed_string_t port; + portid_t port_id; + cmdline_fixed_string_t ext_rxq; + cmdline_fixed_string_t map; + uint16_t sw_queue_id; + uint32_t hw_queue_id; +}; + +cmdline_parse_token_string_t mlx5_cmd_map_ext_rxq_mlx5 = + TOKEN_STRING_INITIALIZER(struct mlx5_cmd_map_ext_rxq, mlx5, "mlx5"); +cmdline_parse_token_string_t mlx5_cmd_map_ext_rxq_port = + TOKEN_STRING_INITIALIZER(struct mlx5_cmd_map_ext_rxq, port, "port"); +cmdline_parse_token_num_t mlx5_cmd_map_ext_rxq_port_id = + TOKEN_NUM_INITIALIZER(struct mlx5_cmd_map_ext_rxq, port_id, RTE_UINT16); +cmdline_parse_token_string_t mlx5_cmd_map_ext_rxq_ext_rxq = + TOKEN_STRING_INITIALIZER(struct mlx5_cmd_map_ext_rxq, ext_rxq, + "ext_rxq"); +cmdline_parse_token_string_t mlx5_cmd_map_ext_rxq_map = + TOKEN_STRING_INITIALIZER(struct mlx5_cmd_map_ext_rxq, map, "map"); +cmdline_parse_token_num_t mlx5_cmd_map_ext_rxq_sw_queue_id = + TOKEN_NUM_INITIALIZER(struct mlx5_cmd_map_ext_rxq, sw_queue_id, + RTE_UINT16); +cmdline_parse_token_num_t mlx5_cmd_map_ext_rxq_hw_queue_id = + TOKEN_NUM_INITIALIZER(struct mlx5_cmd_map_ext_rxq, hw_queue_id, + RTE_UINT32); + +static void +mlx5_cmd_map_ext_rxq_parsed(void *parsed_result, + __rte_unused struct cmdline *cl, + __rte_unused void *data) +{ + struct mlx5_cmd_map_ext_rxq *res = parsed_result; + int ret; + + if (port_id_is_invalid(res->port_id, ENABLED_WARN)) + return; + ret = rte_pmd_mlx5_external_rx_queue_id_map(res->port_id, + res->sw_queue_id, + res->hw_queue_id); + switch (ret) { + case 0: + break; + case -EINVAL: + fprintf(stderr, "invalid ethdev index (%u), out of range\n", + res->sw_queue_id); + break; + case -ENODEV: + fprintf(stderr, "invalid port_id %u\n", res->port_id); + break; + case -ENOTSUP: + fprintf(stderr, "function not implemented or supported\n"); + break; + case -EEXIST: + fprintf(stderr, "mapping with index %u already exists\n", + res->sw_queue_id); + break; + default: + fprintf(stderr, "programming error: (%s)\n", strerror(-ret)); + } +} + +cmdline_parse_inst_t mlx5_cmd_map_ext_rxq = { + .f = mlx5_cmd_map_ext_rxq_parsed, + .data = NULL, + .help_str = "mlx5 port ext_rxq map ", + .tokens = { + (void *)&mlx5_cmd_map_ext_rxq_mlx5, + (void *)&mlx5_cmd_map_ext_rxq_port, + (void *)&mlx5_cmd_map_ext_rxq_port_id, + (void *)&mlx5_cmd_map_ext_rxq_ext_rxq, + (void *)&mlx5_cmd_map_ext_rxq_map, + (void *)&mlx5_cmd_map_ext_rxq_sw_queue_id, + (void *)&mlx5_cmd_map_ext_rxq_hw_queue_id, + NULL, + } +}; + +/* Unmap HW queue index to rte queue index. */ +struct mlx5_cmd_unmap_ext_rxq { + cmdline_fixed_string_t mlx5; + cmdline_fixed_string_t port; + portid_t port_id; + cmdline_fixed_string_t ext_rxq; + cmdline_fixed_string_t unmap; + uint16_t queue_id; +}; + +cmdline_parse_token_string_t mlx5_cmd_unmap_ext_rxq_mlx5 = + TOKEN_STRING_INITIALIZER(struct mlx5_cmd_unmap_ext_rxq, mlx5, "mlx5"); +cmdline_parse_token_string_t mlx5_cmd_unmap_ext_rxq_port = + TOKEN_STRING_INITIALIZER(struct mlx5_cmd_unmap_ext_rxq, port, "port"); +cmdline_parse_token_num_t mlx5_cmd_unmap_ext_rxq_port_id = + TOKEN_NUM_INITIALIZER(struct mlx5_cmd_unmap_ext_rxq, port_id, + RTE_UINT16); +cmdline_parse_token_string_t mlx5_cmd_unmap_ext_rxq_ext_rxq = + TOKEN_STRING_INITIALIZER(struct mlx5_cmd_unmap_ext_rxq, ext_rxq, + "ext_rxq"); +cmdline_parse_token_string_t mlx5_cmd_unmap_ext_rxq_unmap = + TOKEN_STRING_INITIALIZER(struct mlx5_cmd_unmap_ext_rxq, unmap, "unmap"); +cmdline_parse_token_num_t mlx5_cmd_unmap_ext_rxq_queue_id = + TOKEN_NUM_INITIALIZER(struct mlx5_cmd_unmap_ext_rxq, queue_id, + RTE_UINT16); + +static void +mlx5_cmd_unmap_ext_rxq_parsed(void *parsed_result, + __rte_unused struct cmdline *cl, + __rte_unused void *data) +{ + struct mlx5_cmd_unmap_ext_rxq *res = parsed_result; + int ret; + + if (port_id_is_invalid(res->port_id, ENABLED_WARN)) + return; + ret = rte_pmd_mlx5_external_rx_queue_id_unmap(res->port_id, + res->queue_id); + switch (ret) { + case 0: + break; + case -EINVAL: + fprintf(stderr, "invalid rte_flow index (%u), " + "out of range, doesn't exist or still referenced\n", + res->queue_id); + break; + case -ENODEV: + fprintf(stderr, "invalid port_id %u\n", res->port_id); + break; + case -ENOTSUP: + fprintf(stderr, "function not implemented or supported\n"); + break; + default: + fprintf(stderr, "programming error: (%s)\n", strerror(-ret)); + } +} + +cmdline_parse_inst_t mlx5_cmd_unmap_ext_rxq = { + .f = mlx5_cmd_unmap_ext_rxq_parsed, + .data = NULL, + .help_str = "mlx5 port ext_rxq unmap ", + .tokens = { + (void *)&mlx5_cmd_unmap_ext_rxq_mlx5, + (void *)&mlx5_cmd_unmap_ext_rxq_port, + (void *)&mlx5_cmd_unmap_ext_rxq_port_id, + (void *)&mlx5_cmd_unmap_ext_rxq_ext_rxq, + (void *)&mlx5_cmd_unmap_ext_rxq_unmap, + (void *)&mlx5_cmd_unmap_ext_rxq_queue_id, + NULL, + } +}; + static struct testpmd_driver_commands mlx5_driver_cmds = { .commands = { { @@ -417,6 +569,17 @@ static struct testpmd_driver_commands mlx5_driver_cmds = { "and add \"cmd_fd\" and \"pd_handle\" devargs before attaching\n\n", }, #endif + { + .ctx = &mlx5_cmd_map_ext_rxq, + .help = "mlx5 port (port_id) ext_rxq map (sw_queue_id) (hw_queue_id)\n" + " Map HW queue index (32-bit) to ethdev" + " queue index (16-bit) for external RxQ\n\n", + }, + { + .ctx = &mlx5_cmd_unmap_ext_rxq, + .help = "mlx5 port (port_id) ext_rxq unmap (sw_queue_id)\n" + " Unmap external Rx queue ethdev index mapping\n\n", + }, { .ctx = NULL, }, -- 2.25.1