From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7EF60A0093; Sat, 2 Jul 2022 21:35:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2802B41132; Sat, 2 Jul 2022 21:35:06 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 8B33840E50 for ; Sat, 2 Jul 2022 21:35:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656790504; x=1688326504; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=De9iirH1I8vulsJV057GVhL43i5dhnwiuHlR0iCuvTg=; b=mnyHckA+Hrk3zrFmOkZP8NNuOEZn4q0CkXUDiMOENr/It2r05y0sOmza Zc2uo+B1kn4wI20B5DSrCcLakxizWwFNAdOEqjopzVevk58njH7jO6s/R p0RrkT+07M9LCFu8T33WcS99RfOPPc9QAgbJJlnSII3Q0W1KwgbIgZ3Yi uAN4DHL47m0ad1lwo2iUh/AxTssF/Mnu/oJ3qb+b7RUnvL2CXiK0rFy0a C+fgXvpqN4+1707RJVjqWKgndYDfl825JkaJYf9S2DVYBYXR1/MdOZv0y AkMWyGoTaErGcvtYlB/9v8BE+enJHZ2vrqMhpURZhmlTSilOqnObMOxhJ Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10396"; a="271636912" X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="271636912" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2022 12:35:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,240,1650956400"; d="scan'208";a="648830398" Received: from txanpdk03.an.intel.com ([10.123.117.78]) by fmsmga008.fm.intel.com with ESMTP; 02 Jul 2022 12:35:02 -0700 From: Timothy McDaniel To: jerinj@marvell.com Cc: dev@dpdk.org Subject: [PATCH] doc: update DLB2 documentation Date: Sat, 2 Jul 2022 14:35:00 -0500 Message-Id: <20220702193500.1654078-1-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit updates the dlb2.rst eventdev guide to document the new DLB2 features that were added to dpdk 22.07. 1) CQ Weight 2) Port COS 3) Maximum CQ depth 4) Maximum enqueue depth Signed-off-by: Timothy McDaniel --- doc/guides/eventdevs/dlb2.rst | 67 ++++++++++++++++++++++++++++------- 1 file changed, 54 insertions(+), 13 deletions(-) diff --git a/doc/guides/eventdevs/dlb2.rst b/doc/guides/eventdevs/dlb2.rst index bc53618b53..5b21f13b68 100644 --- a/doc/guides/eventdevs/dlb2.rst +++ b/doc/guides/eventdevs/dlb2.rst @@ -343,23 +343,21 @@ Class of service ~~~~~~~~~~~~~~~~ DLB supports provisioning the DLB bandwidth into 4 classes of service. +A LDB port or range of LDB ports may be configured to use one of the classes. +If a port's COS is not defined, then it will be allocated from class 0, +class 1, class 2, or class 3, in that order, depending on availability. -- Class 4 corresponds to 40% of the DLB hardware bandwidth -- Class 3 corresponds to 30% of the DLB hardware bandwidth -- Class 2 corresponds to 20% of the DLB hardware bandwidth -- Class 1 corresponds to 10% of the DLB hardware bandwidth -- Class 0 corresponds to don't care - -The classes are applied globally to the set of ports contained in this -scheduling domain, which is more appropriate for the bifurcated -PMD than for the PF PMD, since the PF PMD supports just 1 scheduling -domain. - -Class of service can be specified in the devargs, as follows +The sum of the cos_bw values may not exceed 100, and no more than +16 LDB ports may be assigned to a given class of service. If port cos is +not defined on the command line, then each class is assigned 25% of the +bandwidth, and the available load balanced ports are split between the classes. +Per-port class of service and bandwidth can be specified in the devargs, +as follows. .. code-block:: console - --allow ea:00.0,cos=<0..4> + --allow ea:00.0,port_cos=Px-Py:<0-3>,cos_bw=5:10:80:5 + --allow ea:00.0,port_cos=Px:<0-3>,cos_bw=5:10:80:5 Use X86 Vector Instructions ~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -373,3 +371,46 @@ follows .. code-block:: console --allow ea:00.0,vector_opts_enabled= + +Maximum CQ Depth +~~~~~~~~~~~~~~~~ + +DLB supports configuring the maximum depth of a consumer queue (CQ). +The depth must be between 32 and 128, and must be a power of 2. Note +that credit deadlocks may occur as a result of changing the default depth. +To prevent deadlock, the user may also need to configure the maximum +enqueue depth. + + .. code-block:: console + + --allow ea:00.0,max_cq_depth= + +Maximum Enqueue Depth +~~~~~~~~~~~~~~~~~~~~~ + +DLB supports configuring the maximum enqueue depth of a producer port (PP). +The depth must be between 32 and 1024, and must be a power of 2. + + .. code-block:: console + + --allow ea:00.0,max_enqueue_depth= + +QE Weight +~~~~~~~~~ + +DLB supports advanced scheduling mechanisms, such as CQ weight. +Each load balanced CQ has a configurable work capacity (max 256) +which corresponds to the total QE weight DLB will allow to be enqueued +to that consumer. Every load balanced event/QE carries a weight of 0, 2, 4, +or 8 and DLB will increment a (per CQ) load indicator when it schedules a +QE to that CQ. The weight is also stored in the history list. When a +completion arrives, the weight is popped from the history list and used to +decrement the load indicator. This creates a new scheduling condition - a CQ +whose load is equal to or in excess of capacity is not available for traffic. +Note that the weight may not exceed the maximum CQ depth. + + .. code-block:: console + + --allow ea:00.0,cq_weight=all: + --allow ea:00.0,cq_weight=qidA-qidB: + --allow ea:00.0,cq_weight=qid: -- 2.25.1