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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(136003)(346002)(376002)(396003)(36840700001)(46966006)(40470700004)(2906002)(316002)(4326008)(8676002)(70206006)(70586007)(450100002)(478600001)(41300700001)(6666004)(54906003)(26005)(40460700003)(40480700001)(82310400005)(6916009)(55016003)(5660300002)(7696005)(8936002)(36860700001)(86362001)(36756003)(6286002)(81166007)(16526019)(82740400003)(356005)(186003)(2616005)(426003)(336012)(1076003)(47076005)(107886003)(83380400001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2022 10:13:03.1487 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7518c404-b365-4f2b-0300-08da5da5c7fd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4395 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Raja Zidane Negative integrity item refers to condition when the item value mask is set, but value spec is cleared: ... integrity value mask l4_ok value spec 0 ... RTE library defines integrity bits `l3_ok` and `l4_ok` as accumulators for all hardware L3 and L4 integrity verifications respectfully. Hardware `l3_ok` and `l4_ok` integrity bits refer to L3 and L4 network headers only. Integrity bits `l3_ok` and `l4_ok` are not compatible between RTE library and hardware. PMD translations for RTE `l3_ok` are: IPv4: `l3_ok` and `l3_csum_ok` IPv6: `l3_ok` RTE `l4_ok` is translated into PMD `l4_ok` and `l4_csum_ok` bits. Positive IPv4 `l3_ok` flow item configuration is translated into a single matcher that AND corresponding hardware bits. Negative IPv4 `l3_ok` is translated into 2 hardware conditions where each condition probes a single integrity bit: RTE::l3_ok is 0 => MLX5::l3_ok is 0 OR MLX5:l3_csum_ok is 0 MLX5 hardware does not do OR condition in flow rule item. Negative IPv4 `l3_ok` must be translated into 2 flow rules. Similarly negative RTE `l4_ok` condition is also translated into 2 hardware rules. Current PMD roadmap does not allow implicit flow rule split. TODO: extend RTE integrity bits definition to allow match on each hardware integrity bit for accumulated integiry matches. Bugzilla ID: 948 cc: stable@dpdk.org Proposed-off-by: Raja Zidane rzidane@nvidia.com Signed-off-by: Gregory Etelson Acked-by: Matan Azrad Acked-by: Viacheslav Ovsiienko --- v2: fix typo in cc address. v3: V4: fix author and version id. --- doc/guides/nics/mlx5.rst | 5 +++-- drivers/net/mlx5/mlx5_flow_dv.c | 6 ++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 9f2832e284..99734157d0 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -479,14 +479,15 @@ Limitations - Integrity offload is enabled starting from **ConnectX-6 Dx**. - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``. - ``level`` value 0 references outer headers. + - Negative integrity item verification is not supported - Multiple integrity items not supported in a single flow rule. - Flow rule items supplied by application must explicitly specify network headers referred by integrity item. For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header, TCP or UDP, must be in the rule pattern as well:: flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end … - or - flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec 0 / eth / ipv4 proto is udp / end … + + flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec l4_ok / eth / ipv4 proto is udp / end … - Connection tracking: diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 09349a021b..bee9363515 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -6779,6 +6779,12 @@ flow_dv_validate_item_integrity(struct rte_eth_dev *dev, RTE_FLOW_ERROR_TYPE_ITEM, integrity_item, "unsupported integrity filter"); + if ((mask->l3_ok & !spec->l3_ok) || (mask->l4_ok & !spec->l4_ok) || + (mask->ipv4_csum_ok & !spec->ipv4_csum_ok) || + (mask->l4_csum_ok & !spec->l4_csum_ok)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + NULL, "negative integrity flow is not supported"); if (spec->level > 1) { if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) return rte_flow_error_set -- 2.34.1