From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F266A00C5; Tue, 19 Jul 2022 13:11:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F266D40A8A; Tue, 19 Jul 2022 13:11:40 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 0B58241147 for ; Tue, 19 Jul 2022 13:11:38 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26J9unS1016406 for ; Tue, 19 Jul 2022 04:11:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ndNky7p8022JOrGgIqlMh/ZXWGfI/j7b1tJsG37m/TI=; b=JjVFJs0QXkQt6ixx3+rOyPGZcMvPrWhkLwFFaeAVC3y70a5KHAdnr1DNZxzVGvbBh1Z0 fgPe65tec8hgu9VueXxSHLHal0PPO0ONutfxA1HNPORqimg9hBrD3WtONevglpD8SJ72 zPRJ8dZ5dkSnSPYCqSomfUyhHXClWsZyiSyfOnza3vx0bYXdVqUnpzVXLObWV0G3g2xd UEqatcVgKZPuG193N0Lh+2wIJ4vx0yAt2oOQ61Gf/+PhxFrUudkCzD4KIRdUSDPnMt+D PMZzqhwPfYNg/1Fk5eHtWSKhQNfvzw9l5pQuk+Fe201aP7+PJChjUZMcYDiAJbw48VRh sg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3hbvumt74f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 19 Jul 2022 04:11:38 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 19 Jul 2022 04:11:36 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 19 Jul 2022 04:11:36 -0700 Received: from MININT-80QBFE8.corp.innovium.com (unknown [10.28.161.88]) by maili.marvell.com (Postfix) with ESMTP id DBD793F7074; Tue, 19 Jul 2022 04:11:33 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH 2/4] event/cnxk: avoid reading non cached registers Date: Tue, 19 Jul 2022 16:41:23 +0530 Message-ID: <20220719111125.8276-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220719111125.8276-1-pbhagavatula@marvell.com> References: <20220719111125.8276-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: y5si6aeceGwKsUNdR1fRCUXzhFhFKs7U X-Proofpoint-ORIG-GUID: y5si6aeceGwKsUNdR1fRCUXzhFhFKs7U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-18_22,2022-07-19_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Avoid reading non-cached registers in fastpath. PENDSTATE need not be read before tag flush in tx enqueue context as we have additional checks prior to check for pending flushes. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn9k_worker.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index 5782f3ed8f..653c51f616 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -156,6 +156,15 @@ cn9k_sso_hws_dual_forward_event(struct cn9k_sso_hws_dual *dws, uint64_t base, } } +static __rte_always_inline void +cn9k_sso_tx_tag_flush(uint64_t base) +{ + if (unlikely(CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_TAG)) == + SSO_TT_EMPTY)) + return; + plt_write64(0, base + SSOW_LF_GWS_OP_SWTAG_FLUSH); +} + static __rte_always_inline void cn9k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id, const uint32_t tag, const uint32_t flags, @@ -811,7 +820,7 @@ cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd, return 1; } - cnxk_sso_hws_swtag_flush(base); + cn9k_sso_tx_tag_flush(base); return 1; } -- 2.25.1