From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8C46EA00C4; Wed, 27 Jul 2022 11:22:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3472840141; Wed, 27 Jul 2022 11:22:12 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 96034400D7 for ; Wed, 27 Jul 2022 11:22:10 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26R99qAC003411 for ; Wed, 27 Jul 2022 02:22:09 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=QdOBoV1jTz55oU2vLu9PRqpU5SnIicv/iYeMMT88QCs=; b=Y1a/bIhmbgVmM+fXWchQLAXgPiS3nQXnVYoPS0OYLiS9zvb1DYeVG1H4eD7AasK6Bslm WzOjl3ArsTXDSKMurMdNzRPINJiNON/Pd2EFP/RXuBuCKCxxo5N0CI0pRqTVzkFsnwmD YsHnLvUnF1R/+B9ah4Y36K9sqLPafaUu/A5+o64baz4eNVVNQUZk/+nzH3K4BdOsu/La 2qOjaJR0Yr44sTvpL58uB8cryE5RgVgk666vA2hwsQxL3pCDBRLFVZT1KM7C62BjlxfV JKq5eTxnLEc0cASeOZtk0ycaIwYEF/ktuoqCPS/GssDys801ofN/KT43rSIf16qY8O9q Dg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3hk2fy80uj-12 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 27 Jul 2022 02:22:09 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Jul 2022 02:21:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Jul 2022 02:21:41 -0700 Received: from setup-1.caveonetworks.com (unknown [10.106.27.161]) by maili.marvell.com (Postfix) with ESMTP id 6F44E3F707E; Wed, 27 Jul 2022 02:21:41 -0700 (PDT) From: Sathesh Edara To: , , , "Radha Mohan Chintakuntla" , Veerasenareddy Burru CC: Subject: [PATCH v2 2/3] net/octeon_ep: support basic stats Date: Wed, 27 Jul 2022 02:21:33 -0700 Message-ID: <20220727092134.141530-3-sedara@marvell.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220727092134.141530-1-sedara@marvell.com> References: <20220727092134.141530-1-sedara@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: XdpdI0XohfWcfPmpd7KnRBOwz-bZUp1m X-Proofpoint-GUID: XdpdI0XohfWcfPmpd7KnRBOwz-bZUp1m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-26_07,2022-07-26_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added functionality to fetch and reset ethdev stats. Signed-off-by: Sathesh Edara --- doc/guides/nics/features/octeon_ep.ini | 1 + drivers/net/octeon_ep/otx_ep_ethdev.c | 52 ++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/doc/guides/nics/features/octeon_ep.ini b/doc/guides/nics/features/octeon_ep.ini index 141d918466..b304ff8877 100644 --- a/doc/guides/nics/features/octeon_ep.ini +++ b/doc/guides/nics/features/octeon_ep.ini @@ -8,4 +8,5 @@ Speed capabilities = P SR-IOV = Y Linux = Y x86-64 = Y +Basic stats = Y Usage doc = Y diff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c index 806add246b..cb45bd7a8a 100644 --- a/drivers/net/octeon_ep/otx_ep_ethdev.c +++ b/drivers/net/octeon_ep/otx_ep_ethdev.c @@ -337,6 +337,56 @@ otx_ep_tx_queue_release(struct rte_eth_dev *dev, uint16_t q_no) otx_ep_delete_iqs(tq->otx_ep_dev, tq->q_no); } +static int +otx_ep_dev_stats_reset(struct rte_eth_dev *dev) +{ + struct otx_ep_device *otx_epvf = OTX_EP_DEV(dev); + uint32_t i; + + for (i = 0; i < otx_epvf->nb_tx_queues; i++) + memset(&otx_epvf->instr_queue[i]->stats, 0, + sizeof(struct otx_ep_iq_stats)); + + for (i = 0; i < otx_epvf->nb_rx_queues; i++) + memset(&otx_epvf->droq[i]->stats, 0, + sizeof(struct otx_ep_droq_stats)); + + return 0; +} + +static int +otx_ep_dev_stats_get(struct rte_eth_dev *eth_dev, + struct rte_eth_stats *stats) +{ + struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev); + struct otx_ep_iq_stats *ostats; + struct otx_ep_droq_stats *istats; + uint32_t i; + + memset(stats, 0, sizeof(struct rte_eth_stats)); + + for (i = 0; i < otx_epvf->nb_tx_queues; i++) { + ostats = &otx_epvf->instr_queue[i]->stats; + stats->q_opackets[i] = ostats->tx_pkts; + stats->q_obytes[i] = ostats->tx_bytes; + stats->opackets += ostats->tx_pkts; + stats->obytes += ostats->tx_bytes; + stats->oerrors += ostats->instr_dropped; + } + for (i = 0; i < otx_epvf->nb_rx_queues; i++) { + istats = &otx_epvf->droq[i]->stats; + stats->q_ipackets[i] = istats->pkts_received; + stats->q_ibytes[i] = istats->bytes_received; + stats->q_errors[i] = istats->rx_err; + stats->ipackets += istats->pkts_received; + stats->ibytes += istats->bytes_received; + stats->imissed += istats->rx_alloc_failure; + stats->ierrors += istats->rx_err; + stats->rx_nombuf += istats->rx_alloc_failure; + } + return 0; +} + /* Define our ethernet definitions */ static const struct eth_dev_ops otx_ep_eth_dev_ops = { .dev_configure = otx_ep_dev_configure, @@ -347,6 +397,8 @@ static const struct eth_dev_ops otx_ep_eth_dev_ops = { .tx_queue_setup = otx_ep_tx_queue_setup, .tx_queue_release = otx_ep_tx_queue_release, .dev_infos_get = otx_ep_dev_info_get, + .stats_get = otx_ep_dev_stats_get, + .stats_reset = otx_ep_dev_stats_reset, }; static int -- 2.36.1