From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>
Cc: <jerinj@marvell.com>, <dev@dpdk.org>,
Rakesh Kudurumalla <rkudurumalla@marvell.com>
Subject: [PATCH 21/23] common/cnxk: add support for CPT second pass
Date: Wed, 10 Aug 2022 00:19:05 +0530 [thread overview]
Message-ID: <20220809184908.24030-21-ndabilpuram@marvell.com> (raw)
In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com>
From: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Added mailbox for masking and setting nix_rq_ctx
parameters and enabling rq masking in ipsec_cfg1
so second pass is applied to all rq's
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
drivers/common/cnxk/hw/nix.h | 4 +-
drivers/common/cnxk/roc_mbox.h | 23 ++++++++++-
drivers/common/cnxk/roc_nix_inl.c | 81 +++++++++++++++++++++++++++++++++++++++
3 files changed, 106 insertions(+), 2 deletions(-)
diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h
index 5863e35..a535264 100644
--- a/drivers/common/cnxk/hw/nix.h
+++ b/drivers/common/cnxk/hw/nix.h
@@ -1242,7 +1242,9 @@ struct nix_cn10k_rq_ctx_s {
uint64_t ipsech_ena : 1;
uint64_t ena_wqwd : 1;
uint64_t cq : 20;
- uint64_t rsvd_36_24 : 13;
+ uint64_t rsvd_34_24 : 11;
+ uint64_t port_ol4_dis : 1;
+ uint64_t port_il4_dis : 1;
uint64_t lenerr_dis : 1;
uint64_t csum_il4_dis : 1;
uint64_t csum_ol4_dis : 1;
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 912de11..688c70b 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -265,7 +265,9 @@ struct mbox_msghdr {
msg_rsp) \
M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp) \
M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
- msg_req, nix_inline_ipsec_cfg)
+ msg_req, nix_inline_ipsec_cfg) \
+ M(NIX_LF_INLINE_RQ_CFG, 0x8024, nix_lf_inline_rq_cfg, \
+ nix_rq_cpt_field_mask_cfg_req, msg_rsp)
/* Messages initiated by AF (range 0xC00 - 0xDFF) */
#define MBOX_UP_CGX_MESSAGES \
@@ -1088,6 +1090,25 @@ struct nix_mark_format_cfg_rsp {
uint8_t __io mark_format_idx;
};
+struct nix_rq_cpt_field_mask_cfg_req {
+ struct mbox_msghdr hdr;
+#define RQ_CTX_MASK_MAX 6
+ union {
+ uint64_t __io rq_ctx_word_set[RQ_CTX_MASK_MAX];
+ struct nix_cn10k_rq_ctx_s rq_set;
+ };
+ union {
+ uint64_t __io rq_ctx_word_mask[RQ_CTX_MASK_MAX];
+ struct nix_cn10k_rq_ctx_s rq_mask;
+ };
+ struct nix_lf_rx_ipec_cfg1_req {
+ uint32_t __io spb_cpt_aura;
+ uint8_t __io rq_mask_enable;
+ uint8_t __io spb_cpt_sizem1;
+ uint8_t __io spb_cpt_enable;
+ } ipsec_cfg1;
+};
+
struct nix_lso_format_cfg {
struct mbox_msghdr hdr;
uint64_t __io field_mask;
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index be0b806..cdf31b1 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -416,6 +416,70 @@ roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags)
return roc_cpt_rxc_time_cfg(roc_cpt, &cfg);
}
+static int
+nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)
+{
+ struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+ struct nix_rq_cpt_field_mask_cfg_req *msk_req;
+ struct idev_cfg *idev = idev_get_cfg();
+ struct mbox *mbox = (&nix->dev)->mbox;
+ struct idev_nix_inl_cfg *inl_cfg;
+ uint64_t aura_handle;
+ int rc = -ENOSPC;
+ int i;
+
+ if (!idev)
+ return rc;
+
+ inl_cfg = &idev->inl_cfg;
+ msk_req = mbox_alloc_msg_nix_lf_inline_rq_cfg(mbox);
+ if (msk_req == NULL)
+ return rc;
+
+ for (i = 0; i < RQ_CTX_MASK_MAX; i++)
+ msk_req->rq_ctx_word_mask[i] = 0xFFFFFFFFFFFFFFFF;
+
+ msk_req->rq_set.len_ol3_dis = 1;
+ msk_req->rq_set.len_ol4_dis = 1;
+ msk_req->rq_set.len_il3_dis = 1;
+
+ msk_req->rq_set.len_il4_dis = 1;
+ msk_req->rq_set.csum_ol4_dis = 1;
+ msk_req->rq_set.csum_il4_dis = 1;
+
+ msk_req->rq_set.lenerr_dis = 1;
+ msk_req->rq_set.port_ol4_dis = 1;
+ msk_req->rq_set.port_il4_dis = 1;
+
+ msk_req->rq_set.lpb_drop_ena = 0;
+ msk_req->rq_set.spb_drop_ena = 0;
+ msk_req->rq_set.xqe_drop_ena = 0;
+
+ msk_req->rq_mask.len_ol3_dis = ~(msk_req->rq_set.len_ol3_dis);
+ msk_req->rq_mask.len_ol4_dis = ~(msk_req->rq_set.len_ol4_dis);
+ msk_req->rq_mask.len_il3_dis = ~(msk_req->rq_set.len_il3_dis);
+
+ msk_req->rq_mask.len_il4_dis = ~(msk_req->rq_set.len_il4_dis);
+ msk_req->rq_mask.csum_ol4_dis = ~(msk_req->rq_set.csum_ol4_dis);
+ msk_req->rq_mask.csum_il4_dis = ~(msk_req->rq_set.csum_il4_dis);
+
+ msk_req->rq_mask.lenerr_dis = ~(msk_req->rq_set.lenerr_dis);
+ msk_req->rq_mask.port_ol4_dis = ~(msk_req->rq_set.port_ol4_dis);
+ msk_req->rq_mask.port_il4_dis = ~(msk_req->rq_set.port_il4_dis);
+
+ msk_req->rq_mask.lpb_drop_ena = ~(msk_req->rq_set.lpb_drop_ena);
+ msk_req->rq_mask.spb_drop_ena = ~(msk_req->rq_set.spb_drop_ena);
+ msk_req->rq_mask.xqe_drop_ena = ~(msk_req->rq_set.xqe_drop_ena);
+
+ aura_handle = roc_npa_zero_aura_handle();
+ msk_req->ipsec_cfg1.spb_cpt_aura = roc_npa_aura_handle_to_aura(aura_handle);
+ msk_req->ipsec_cfg1.rq_mask_enable = enable;
+ msk_req->ipsec_cfg1.spb_cpt_sizem1 = inl_cfg->buf_sz;
+ msk_req->ipsec_cfg1.spb_cpt_enable = enable;
+
+ return mbox_process(mbox);
+}
+
int
roc_nix_inl_inb_init(struct roc_nix *roc_nix)
{
@@ -472,6 +536,14 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)
nix->need_meta_aura = true;
idev->inl_cfg.refs++;
}
+
+ if (roc_model_is_cn10kb_a0()) {
+ rc = nix_inl_rq_mask_cfg(roc_nix, true);
+ if (rc) {
+ plt_err("Failed to get rq mask rc=%d", rc);
+ return rc;
+ }
+ }
nix->inl_inb_ena = true;
return 0;
}
@@ -481,6 +553,7 @@ roc_nix_inl_inb_fini(struct roc_nix *roc_nix)
{
struct idev_cfg *idev = idev_get_cfg();
struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+ int rc;
if (!nix->inl_inb_ena)
return 0;
@@ -496,6 +569,14 @@ roc_nix_inl_inb_fini(struct roc_nix *roc_nix)
nix_inl_meta_aura_destroy();
}
+ if (roc_model_is_cn10kb_a0()) {
+ rc = nix_inl_rq_mask_cfg(roc_nix, false);
+ if (rc) {
+ plt_err("Failed to get rq mask rc=%d", rc);
+ return rc;
+ }
+ }
+
/* Flush Inbound CTX cache entries */
roc_nix_cpt_ctx_cache_sync(roc_nix);
--
2.8.4
next prev parent reply other threads:[~2022-08-09 18:51 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-09 18:48 [PATCH 01/23] common/cnxk: fix part value for cn10k Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 02/23] common/cnxk: add cn10ka A1 platform Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 03/23] common/cnxk: update inbound inline IPsec config mailbox Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 04/23] net/cnxk: fix missing fc wait for outbound path in vec mode Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 05/23] common/cnxk: limit meta aura workaround to CN10K A0 Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 06/23] common/cnxk: delay inline device RQ enable to dev start Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 07/23] common/cnxk: reserve aura zero on cn10ka NPA Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 08/23] common/cnxk: add support to set NPA buf type Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 09/23] common/cnxk: update attributes to pools used by NIX Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 10/23] common/cnxk: support zero aura for inline inbound meta Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 11/23] net/cnxk: support for zero aura for inline meta Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 12/23] common/cnxk: avoid the use of platform specific APIs Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 13/23] net/cnxk: use full context IPsec structures in fp Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 14/23] net/cnxk: add crypto capabilities for HMAC-SHA2 Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 15/23] common/cnxk: enable aging on CN10K platform Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 16/23] common/cnxk: updated shaper profile with red algorithm Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 17/23] common/cnxk: add 98xx A1 platform Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 18/23] net/cnxk: enable additional ciphers for inline Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 19/23] net/cnxk: enable 3des-cbc cipher capability Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 20/23] net/cnxk: skip PFC configuration on LBK Nithin Dabilpuram
2022-08-09 18:49 ` Nithin Dabilpuram [this message]
2022-08-09 18:49 ` [PATCH 22/23] common/cnxk: add CQ limit associated with SQ Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 23/23] common/cnxk: support Tx compl event via RQ to CQ mapping Nithin Dabilpuram
2022-08-30 4:51 ` [PATCH 01/23] common/cnxk: fix part value for cn10k Jerin Jacob
2022-08-30 5:16 ` [EXT] " Nithin Kumar Dabilpuram
2022-09-05 13:31 ` [PATCH v2 01/31] cnxk/net: add fc check in vector event Tx path Nithin Dabilpuram
2022-09-05 13:31 ` [PATCH v2 02/31] common/cnxk: fix part value for cn10k Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 03/31] common/cnxk: add cn10ka A1 platform Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 04/31] common/cnxk: update inbound inline IPsec config mailbox Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 05/31] net/cnxk: fix missing fc wait for outbound path in vec mode Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 06/31] common/cnxk: limit meta aura workaround to CN10K A0 Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 07/31] common/cnxk: delay inline device RQ enable to dev start Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 08/31] common/cnxk: reserve aura zero on cn10ka NPA Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 09/31] common/cnxk: add support to set NPA buf type Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 10/31] common/cnxk: update attributes to pools used by NIX Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 11/31] common/cnxk: support zero aura for inline inbound meta Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 12/31] net/cnxk: support for zero aura for inline meta Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 13/31] common/cnxk: avoid the use of platform specific APIs Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 14/31] net/cnxk: use full context IPsec structures in fp Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 15/31] net/cnxk: add crypto capabilities for HMAC-SHA2 Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 16/31] common/cnxk: enable aging on CN10K platform Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 17/31] common/cnxk: updated shaper profile with red algorithm Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 18/31] common/cnxk: add 98xx A1 platform Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 19/31] net/cnxk: enable additional ciphers for inline Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 20/31] net/cnxk: enable 3des-cbc cipher capability Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 21/31] net/cnxk: skip PFC configuration on LBK Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 22/31] common/cnxk: add support for CPT second pass Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 23/31] common/cnxk: add CQ limit associated with SQ Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 24/31] common/cnxk: support Tx compl event via RQ to CQ mapping Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 25/31] event/cnxk: wait for CPT fc on wqe path Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 26/31] net/cnxk: limit port specific SA table size Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 27/31] net/cnxk: add support for crypto cipher DES-CBC Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 28/31] net/cnxk: Add support for crypto auth alg MD5 Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 29/31] net/cnxk: enable esn and antireplay support Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 30/31] common/cnxk: dump device basic info to file Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 31/31] net/cnxk: dumps device private information Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 01/32] net/cnxk: add eth port specific PTP enable Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 02/32] cnxk/net: add fc check in vector event Tx path Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 03/32] common/cnxk: fix part value for cn10k Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 04/32] common/cnxk: add cn10ka A1 platform Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 05/32] common/cnxk: update inbound inline IPsec config mailbox Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 06/32] net/cnxk: fix missing fc wait for outbound path in vec mode Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 07/32] common/cnxk: limit meta aura workaround to CN10K A0 Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 08/32] common/cnxk: delay inline device RQ enable to dev start Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 09/32] common/cnxk: reserve aura zero on cn10ka NPA Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 10/32] common/cnxk: add support to set NPA buf type Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 11/32] common/cnxk: update attributes to pools used by NIX Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 12/32] common/cnxk: support zero aura for inline inbound meta Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 13/32] net/cnxk: support for zero aura for inline meta Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 14/32] common/cnxk: avoid the use of platform specific APIs Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 15/32] net/cnxk: use full context IPsec structures in fp Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 16/32] net/cnxk: add crypto capabilities for HMAC-SHA2 Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 17/32] common/cnxk: enable aging on CN10K platform Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 18/32] common/cnxk: updated shaper profile with red algorithm Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 19/32] common/cnxk: add 98xx A1 platform Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 20/32] net/cnxk: enable additional ciphers for inline Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 21/32] net/cnxk: enable 3des-cbc cipher capability Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 22/32] net/cnxk: skip PFC configuration on LBK Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 23/32] common/cnxk: add support for CPT second pass Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 24/32] common/cnxk: add CQ limit associated with SQ Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 25/32] common/cnxk: support Tx compl event via RQ to CQ mapping Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 26/32] event/cnxk: wait for CPT fc on wqe path Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 27/32] net/cnxk: limit port specific SA table size Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 28/32] net/cnxk: add support for crypto cipher DES-CBC Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 29/32] net/cnxk: add support for crypto auth alg MD5 Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 30/32] net/cnxk: enable esn and antireplay support Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 31/32] common/cnxk: dump device basic info to file Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 32/32] net/cnxk: dumps device private information Nithin Dabilpuram
2022-09-16 11:36 ` Jerin Jacob
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220809184908.24030-21-ndabilpuram@marvell.com \
--to=ndabilpuram@marvell.com \
--cc=dev@dpdk.org \
--cc=jerinj@marvell.com \
--cc=kirankumark@marvell.com \
--cc=rkudurumalla@marvell.com \
--cc=skori@marvell.com \
--cc=skoteshwar@marvell.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).