From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 634E4A00C3; Mon, 15 Aug 2022 01:04:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0F63E42BB3; Mon, 15 Aug 2022 01:03:36 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 44ACF42B88 for ; Mon, 15 Aug 2022 01:03:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660518214; x=1692054214; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+XtH/byjHTEF9mE0aq56QVmKojzZ8NOBMXPtQFGiHc4=; b=TMndhRyZ8/ZTyQKt9St+UpRj3G9IdAF4fzy170KpIo3pbjf5Vm4zY9hK o9Xw7J/UDC7rjYHa60VeZmhamRhpr6uTYD6HFpGJK+ZI1uDUdTj4/Q0Q6 K6gu3R+XVjKfsC79N20pRQcjY1pWR4yxEahI3GBow1PHTGAWd7U27ytwI PeSegzm9LkCGxDNgZxv2K3jDoeTHitw16D4tyX2Y2NaMjgjPwuj2pDNW0 9xYCzeMBaKoTuMoXMtym5WtvfabdV5Jya2ePX7cNRxUH0GZp4410m8Or+ Dus1b/zSSDhaep6fHiWmEJ/9g/OaKyCM6i1sExdTLHpzA3HloMvE6j2Co g==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="289427566" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="289427566" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:03:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="934296605" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:03:32 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Sergey Temerkhanov Subject: [PATCH 14/70] net/ice/base: add 56G PHY register definitions Date: Mon, 15 Aug 2022 03:12:10 -0400 Message-Id: <20220815071306.2910599-15-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815071306.2910599-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add 56G PHY register address definitions to facilitate 56G PHY support. Signed-off-by: Sergey Temerkhanov Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_ptp_hw.h | 75 +++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 9cc3436aa8..ecb79eaea9 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -482,5 +482,80 @@ bool ice_is_pca9575_present(struct ice_hw *hw); #define ICE_E810T_SMA_MIN_BIT 3 #define ICE_E810T_SMA_MAX_BIT 7 #define ICE_E810T_P1_OFFSET 8 +/* 56G PHY quad register base addresses */ +#define ICE_PHY0_BASE 0x092000 +#define ICE_PHY1_BASE 0x126000 +#define ICE_PHY2_BASE 0x1BA000 +#define ICE_PHY3_BASE 0x24E000 +#define ICE_PHY4_BASE 0x2E2000 + +/* Timestamp memory */ +#define PHY_PTP_LANE_ADDR_STEP 0x98 + +#define PHY_PTP_MEM_START 0x1000 +#define PHY_PTP_MEM_LANE_STEP 0x04A0 +#define PHY_PTP_MEM_LOCATIONS 0x40 + +/* Number of PHY ports */ +#define ICE_NUM_PHY_PORTS 5 +/* Timestamp PHY incval registers */ +#define PHY_REG_TIMETUS_L 0x8 +#define PHY_REG_TIMETUS_U 0xC + +/* Timestamp init registers */ +#define PHY_REG_RX_TIMER_INC_PRE_L 0x64 +#define PHY_REG_RX_TIMER_INC_PRE_U 0x68 + +#define PHY_REG_TX_TIMER_INC_PRE_L 0x44 +#define PHY_REG_TX_TIMER_INC_PRE_U 0x48 + +/* Timestamp match and adjust target registers */ +#define PHY_REG_RX_TIMER_CNT_ADJ_L 0x6C +#define PHY_REG_RX_TIMER_CNT_ADJ_U 0x70 + +#define PHY_REG_TX_TIMER_CNT_ADJ_L 0x4C +#define PHY_REG_TX_TIMER_CNT_ADJ_U 0x50 + +/* Timestamp command registers */ +#define PHY_REG_TX_TMR_CMD 0x40 +#define PHY_REG_RX_TMR_CMD 0x60 + +/* Phy offset ready registers */ +#define PHY_REG_TX_OFFSET_READY 0x54 +#define PHY_REG_RX_OFFSET_READY 0x74 +/* Phy total offset registers */ +#define PHY_REG_TOTAL_TX_OFFSET_L 0x38 +#define PHY_REG_TOTAL_TX_OFFSET_U 0x3C + +#define PHY_REG_TOTAL_RX_OFFSET_L 0x58 +#define PHY_REG_TOTAL_RX_OFFSET_U 0x5C + +/* Timestamp capture registers */ +#define PHY_REG_TX_CAPTURE_L 0x78 +#define PHY_REG_TX_CAPTURE_U 0x7C + +#define PHY_REG_RX_CAPTURE_L 0x8C +#define PHY_REG_RX_CAPTURE_U 0x90 + +/* Memory status registers */ +#define PHY_REG_TX_MEMORY_STATUS_L 0x80 +#define PHY_REG_TX_MEMORY_STATUS_U 0x84 + +/* Interrupt config register */ +#define PHY_REG_TS_INT_CONFIG 0x88 + +#define PHY_PTP_INT_STATUS 0x7FD140 + +#define PHY_TS_INT_CONFIG_THRESHOLD_S 0 +#define PHY_TS_INT_CONFIG_THRESHOLD_M MAKEMASK(0x3F, 0) +#define PHY_TS_INT_CONFIG_ENA_S 6 +#define PHY_TS_INT_CONFIG_ENA_M BIT(6) + +/* Macros to derive offsets for TimeStampLow and TimeStampHigh */ +#define PHY_TSTAMP_L(x) (((x) * 8) + 0) +#define PHY_TSTAMP_U(x) (((x) * 8) + 4) + +#define PHY_REG_REVISION 0x85000 +#define PHY_REVISION_ETH56G 0x10200 #endif /* _ICE_PTP_HW_H_ */ -- 2.31.1