From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 44C40A00C3; Mon, 15 Aug 2022 01:07:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 04D8842C5F; Mon, 15 Aug 2022 01:04:21 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id B4B1942B9D for ; Mon, 15 Aug 2022 01:04:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660518258; x=1692054258; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f05nU9uoKaLEJG9EAfsPmRXU7kK+H7Bl2EiqbmgXYsw=; b=P19fSVi96L7hnlOpsw9je9THCzOC8IiJnTpA/Cmcg3Gkd6jL7Oc/n4sG Z7clnZ82PRzbwO+NeOwDoIYKMMvZbuebJezkjVoaZETyrag6nbFeOFM0c vo4azGTHCtJ0j+7FYI5B0cI3w82lFAOq5uahcTNbg8iJ4xZ/mP1tSDTBO YpLQLEp+j0AWEeNLFY7bRDUCiMCjb6eIwwM0UHkO9lxHruFUqgCNBu4Pw PvXWGRqrct7fOkgTHBKdeBrrTv+0CbePGq2W7eQiHXlK7GJ+tABQ/wfrO gkKVT/gAVwQp6igREGoaKDJkJhgBowONY4UQNw3ILSb/FLfRYvidSTOwg g==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="289427625" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="289427625" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:04:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="934296799" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:04:17 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Jacob Keller Subject: [PATCH 43/70] net/ice/base: move functions Date: Mon, 15 Aug 2022 03:12:39 -0400 Message-Id: <20220815071306.2910599-44-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815071306.2910599-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Move function ice_ptp_set_vernier_wl and ice_ptp_src_cmd to align with kernel driver. Signed-off-by: Jacob Keller Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_ptp_hw.c | 130 +++++++++++++++--------------- 1 file changed, 66 insertions(+), 64 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 712b7dedfb..dfb9d08224 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -381,6 +381,47 @@ static enum ice_status ice_init_cgu_e822(struct ice_hw *hw) return ICE_SUCCESS; } +/** + * ice_ptp_src_cmd - Prepare source timer for a timer command + * @hw: pointer to HW structure + * @cmd: Timer command + * + * Prepare the source timer for an upcoming timer sync command. + */ +void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) +{ + u32 cmd_val; + u8 tmr_idx; + + tmr_idx = ice_get_ptp_src_clock_index(hw); + cmd_val = tmr_idx << SEL_CPK_SRC; + + switch (cmd) { + case ICE_PTP_INIT_TIME: + cmd_val |= GLTSYN_CMD_INIT_TIME; + break; + case ICE_PTP_INIT_INCVAL: + cmd_val |= GLTSYN_CMD_INIT_INCVAL; + break; + case ICE_PTP_ADJ_TIME: + cmd_val |= GLTSYN_CMD_ADJ_TIME; + break; + case ICE_PTP_ADJ_TIME_AT_TIME: + cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME; + break; + case ICE_PTP_READ_TIME: + cmd_val |= GLTSYN_CMD_READ_TIME; + break; + case ICE_PTP_NOP: + break; + default: + ice_warn(hw, "Unknown timer command %u\n", cmd); + return; + } + + wr32(hw, GLTSYN_CMD, cmd_val); +} + /** * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands * @hw: pointer to HW struct @@ -2365,6 +2406,31 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) return ICE_SUCCESS; } +/** + * ice_ptp_set_vernier_wl - Set the window length for vernier calibration + * @hw: pointer to the HW struct + * + * Set the window length used for the vernier port calibration process. + */ +enum ice_status ice_ptp_set_vernier_wl(struct ice_hw *hw) +{ + u8 port; + + for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + enum ice_status status; + + status = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL, + PTP_VERNIER_WL, true); + if (status) { + ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, status %d\n", + port, status); + return status; + } + } + + return ICE_SUCCESS; +} + /** * ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization * @hw: pointer to HW struct @@ -2817,31 +2883,6 @@ ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, * port. */ -/** - * ice_ptp_set_vernier_wl - Set the window length for vernier calibration - * @hw: pointer to the HW struct - * - * Set the window length used for the vernier port calibration process. - */ -enum ice_status ice_ptp_set_vernier_wl(struct ice_hw *hw) -{ - u8 port; - - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { - enum ice_status status; - - status = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL, - PTP_VERNIER_WL, true); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, status %d\n", - port, status); - return status; - } - } - - return ICE_SUCCESS; -} - /** * ice_phy_get_speed_and_fec_e822 - Get link speed and FEC based on serdes mode * @hw: pointer to HW struct @@ -4829,45 +4870,6 @@ void ice_ptp_unlock(struct ice_hw *hw) wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); } -/** - * ice_ptp_src_cmd - Prepare source timer for a timer command - * @hw: pointer to HW structure - * @cmd: Timer command - * - * Prepare the source timer for an upcoming timer sync command. - */ -void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) -{ - u32 cmd_val; - u8 tmr_idx; - - tmr_idx = ice_get_ptp_src_clock_index(hw); - cmd_val = tmr_idx << SEL_CPK_SRC; - - switch (cmd) { - case ICE_PTP_INIT_TIME: - cmd_val |= GLTSYN_CMD_INIT_TIME; - break; - case ICE_PTP_INIT_INCVAL: - cmd_val |= GLTSYN_CMD_INIT_INCVAL; - break; - case ICE_PTP_ADJ_TIME: - cmd_val |= GLTSYN_CMD_ADJ_TIME; - break; - case ICE_PTP_ADJ_TIME_AT_TIME: - cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME; - break; - case ICE_PTP_READ_TIME: - cmd_val |= GLTSYN_CMD_READ_TIME; - break; - default: - ice_warn(hw, "Unknown timer command %u\n", cmd); - return; - } - - wr32(hw, GLTSYN_CMD, cmd_val); -} - /** * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command * @hw: pointer to HW struct -- 2.31.1