From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B5030A00C3; Mon, 15 Aug 2022 01:08:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 55A1542CA8; Mon, 15 Aug 2022 01:04:35 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id BF07E42C17 for ; Mon, 15 Aug 2022 01:04:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660518271; x=1692054271; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b1yY/GdEyZdnZphwApBxnYhoaGxN3qYd8Fs4745b+nA=; b=LGviyaY6ba0KvEQEX/w0xFLyOlUL6V1FZ/lR9xwXDh9hJ0t/MVY4fLjf oTkyu2he4EAbtRimzESLpQg2c4W1BGWI9vXgesf1Gvu8YbJof9Wy7JHz3 E5VnZ2fIvW4vbWLudkuKemP+1A81439IiPQfnTUwkSGEzLoRrzV96emi4 Gp6NteovhcYPJfM/wV0fJiZGAdgTwRpR47jSwYj5A7tNcDXnAnWp6MqkQ Z1LcYlkSiDtG1JbV11+fK3ZDrAPP9LwyQDL/Qr+WLYdhK/Cv9LqH6rbK9 p3uSJnrRJfeVrZYFX9EJ3opqegDE+CCOMoII2NL1Ia+FCuWCqdgJ6PCjy A==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="293128783" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="293128783" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:04:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="934296852" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:04:29 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Sergey Temerkhanov Subject: [PATCH 52/70] net/ice/base: clean the main timer command register Date: Mon, 15 Aug 2022 03:12:48 -0400 Message-Id: <20220815071306.2910599-53-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815071306.2910599-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Clean the main timer command register after use to avoid residual command execution, such as re-initialization of the main timer. Signed-off-by: Sergey Temerkhanov Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_ptp_hw.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index dfb9d08224..f5ebf5f328 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -3751,6 +3751,7 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time, /* Issue the sync to start the ICE_PTP_READ_TIME capture */ ice_ptp_exec_tmr_cmd(hw); + ice_ptp_clean_cmd(hw); /* Read the captured PHC time from the shadow time registers */ zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); @@ -3825,6 +3826,7 @@ static enum ice_status ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port) /* Issue the sync to activate the time adjustment */ ice_ptp_exec_tmr_cmd(hw); + ice_ptp_clean_cmd(hw); /* Re-capture the timer values to flush the command registers and * verify that the time was properly adjusted. @@ -3920,6 +3922,7 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) u64 incval; u8 tmr_idx; + ice_ptp_clean_cmd(hw); tmr_idx = ice_get_ptp_src_clock_index(hw); status = ice_stop_phy_timer_e822(hw, port, false); @@ -4913,6 +4916,7 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) * commands synchronously */ ice_ptp_exec_tmr_cmd(hw); + ice_ptp_clean_cmd(hw); return ICE_SUCCESS; } -- 2.31.1