From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 427E2A00C3; Mon, 15 Aug 2022 23:58:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A3E8C42B78; Mon, 15 Aug 2022 23:57:42 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 29BC1427F2 for ; Mon, 15 Aug 2022 23:57:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600655; x=1692136655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g2mMc/CoqosLqfKCunx1ZXcqIRyidxgu9kfrcZlHNvM=; b=jP+aUGTpAJEFKt4vykTcYzJWnBBRfFcBQZ8FC2rXLX/W5LruhPuZC+iC BEt/RcnVPqi4sie9cz9rNRQIBuvf25wqjqXKbUO3YmPheH7iTv+/ubY6S dBPdxD9MVUmatwpPDX3wN9iKa52r/kPh4kQ4OwM3tXmxQrFhqWVD5vMc5 s6+Az3URORYe3IERmGqHnH/YjZYF37DGnza3gNUDAo1latliARbmjsC+B Ka7q1O3y0BJxKdShJRTgETOZS4X83iHun0KK9QMBEvEJLALUQP3WuPRxX EdJhtclGp+YhzucpvhBNQ9F4FqujoESAYH9ykob4hfFQdBrKka3VhCfrL g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862713" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862713" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826043" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:34 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 09/33] baseband/acc100: add LDPC transport block support Date: Mon, 15 Aug 2022 22:52:34 -0700 Message-Id: <20220816055258.107564-10-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add LDPC enqueue functions to handle transport blocks. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/acc100_pmd.h | 1 + drivers/baseband/acc100/rte_acc100_pmd.c | 197 ++++++++++++++++++++++- 2 files changed, 196 insertions(+), 2 deletions(-) diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h index 0c9810ca56..19a1f434bc 100644 --- a/drivers/baseband/acc100/acc100_pmd.h +++ b/drivers/baseband/acc100/acc100_pmd.h @@ -135,6 +135,7 @@ #define ACC100_DEC_OFFSET (80) #define ACC100_EXT_MEM /* Default option with memory external to CPU */ #define ACC100_HARQ_OFFSET_THRESHOLD 1024 +#define ACC100_LIMIT_DL_MUX_BITS 534 /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ #define ACC100_N_ZC_1 66 /* N = 66 Zc for BG 1 */ diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 6c6e3e1072..b0f41f15cb 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -2588,6 +2588,61 @@ enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops, return num; } +/* Enqueue one encode operations for ACC100 device for a partial TB + * all codes blocks have same configuration multiplexed on the same descriptor + */ +static inline void +enqueue_ldpc_enc_part_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, + uint16_t total_enqueued_descs, int16_t num_cbs, uint32_t e, + uint16_t in_len_B, uint32_t out_len_B, uint32_t *in_offset, + uint32_t *out_offset) +{ + + union acc100_dma_desc *desc = NULL; + struct rte_mbuf *output_head, *output; + int i, next_triplet; + struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc; + + + uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_descs) + & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; + acc100_fcw_le_fill(op, &desc->req.fcw_le, num_cbs, e); + + /** This could be done at polling */ + acc100_header_init(&desc->req); + desc->req.numCBs = num_cbs; + + desc->req.m2dlen = 1 + num_cbs; + desc->req.d2mlen = num_cbs; + next_triplet = 1; + + for (i = 0; i < num_cbs; i++) { + desc->req.data_ptrs[next_triplet].address = + rte_pktmbuf_iova_offset(enc->input.data, + *in_offset); + *in_offset += in_len_B; + desc->req.data_ptrs[next_triplet].blen = in_len_B; + next_triplet++; + desc->req.data_ptrs[next_triplet].address = + rte_pktmbuf_iova_offset( + enc->output.data, *out_offset); + *out_offset += out_len_B; + desc->req.data_ptrs[next_triplet].blen = out_len_B; + next_triplet++; + enc->output.length += out_len_B; + output_head = output = enc->output.data; + mbuf_append(output_head, output, out_len_B); + } + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + rte_memdump(stderr, "FCW", &desc->req.fcw_le, + sizeof(desc->req.fcw_le) - 8); + rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc)); +#endif + +} + /* Enqueue one encode operations for ACC100 device in CB mode */ static inline int enqueue_ldpc_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, @@ -2728,6 +2783,76 @@ enqueue_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, return current_enqueued_cbs; } +/* Enqueue one encode operations for ACC100 device in TB mode. + * returns the number of descs used + */ +static inline int +enqueue_ldpc_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, + uint16_t enq_descs, uint8_t cbs_in_tb) +{ +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE + if (validate_ldpc_enc_op(op, q) == -1) { + rte_bbdev_log(ERR, "LDPC encoder validation failed"); + return -EINVAL; + } +#endif + uint8_t num_a, num_b; + uint16_t desc_idx; + uint8_t r = op->ldpc_enc.tb_params.r; + uint8_t cab = op->ldpc_enc.tb_params.cab; + union acc100_dma_desc *desc; + uint16_t init_enq_descs = enq_descs; + uint16_t input_len_B = ((op->ldpc_enc.basegraph == 1 ? 22 : 10) * + op->ldpc_enc.z_c - op->ldpc_enc.n_filler) >> 3; + if (check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + input_len_B -= 3; + + if (r < cab) { + num_a = cab - r; + num_b = cbs_in_tb - cab; + } else { + num_a = 0; + num_b = cbs_in_tb - r; + } + uint32_t in_offset = 0, out_offset = 0; + + while (num_a > 0) { + uint32_t e = op->ldpc_enc.tb_params.ea; + uint32_t out_len_B = (e + 7) >> 3; + uint8_t enq = RTE_MIN(num_a, ACC100_MUX_5GDL_DESC); + num_a -= enq; + enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B, + out_len_B, &in_offset, &out_offset); + enq_descs++; + } + while (num_b > 0) { + uint32_t e = op->ldpc_enc.tb_params.eb; + uint32_t out_len_B = (e + 7) >> 3; + uint8_t enq = RTE_MIN(num_b, ACC100_MUX_5GDL_DESC); + num_b -= enq; + enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B, + out_len_B, &in_offset, &out_offset); + enq_descs++; + } + + uint16_t return_descs = enq_descs - init_enq_descs; + /* Keep total number of CBs in first TB */ + desc_idx = ((q->sw_ring_head + init_enq_descs) + & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; + desc->req.cbs_in_tb = return_descs; /** Actual number of descriptors */ + desc->req.op_addr = op; + + /* Set SDone on last CB descriptor for TB mode. */ + desc_idx = ((q->sw_ring_head + enq_descs - 1) + & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; + desc->req.sdone_enable = 1; + desc->req.irq_enable = q->irq_enable; + desc->req.op_addr = op; + return return_descs; +} + #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validates turbo decoder parameters */ static inline int @@ -3302,7 +3427,10 @@ enqueue_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, uint16_t current_enqueued_cbs = 0; #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE - /* Validate op structure */ + if (cbs_in_tb == 0) { + rte_bbdev_log(ERR, "Turbo decoder invalid number of CBs"); + return -EINVAL; + } if (validate_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo decoder validation rejected"); return -EINVAL; @@ -3389,6 +3517,32 @@ enqueue_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, return current_enqueued_cbs; } +/* Calculates number of CBs in processed encoder TB based on 'r' and input + * length. + */ +static inline uint8_t +get_num_cbs_in_tb_ldpc_enc(struct rte_bbdev_op_ldpc_enc *ldpc_enc) +{ + uint8_t c, r, crc24_bits = 0; + uint16_t k = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c + - ldpc_enc->n_filler; + uint8_t cbs_in_tb = 0; + int32_t length; + + length = ldpc_enc->input.length; + r = ldpc_enc->tb_params.r; + c = ldpc_enc->tb_params.c; + crc24_bits = 0; + if (check_bit(ldpc_enc->op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + crc24_bits = 24; + while (length > 0 && r < c) { + length -= (k - crc24_bits) >> 3; + r++; + cbs_in_tb++; + } + return cbs_in_tb; +} + /* Calculates number of CBs in processed encoder TB based on 'r' and input * length. */ @@ -3670,6 +3824,45 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data, return i; } +/* Enqueue LDPC encode operations for ACC100 device in TB mode. */ +static uint16_t +acc100_enqueue_ldpc_enc_tb(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_enc_op **ops, uint16_t num) +{ + struct acc100_queue *q = q_data->queue_private; + int32_t avail = acc100_ring_avail_enq(q); + uint16_t i, enqueued_descs = 0; + uint8_t cbs_in_tb; + int descs_used; + + for (i = 0; i < num; ++i) { + cbs_in_tb = get_num_cbs_in_tb_ldpc_enc(&ops[i]->ldpc_enc); + /* Check if there are available space for further processing */ + if (unlikely(avail - cbs_in_tb < 0)) { + acc100_enqueue_ring_full(q_data); + break; + } + descs_used = enqueue_ldpc_enc_one_op_tb(q, ops[i], + enqueued_descs, cbs_in_tb); + if (descs_used < 0) { + acc100_enqueue_invalid(q_data); + break; + } + enqueued_descs += descs_used; + avail -= descs_used; + } + if (unlikely(enqueued_descs == 0)) + return 0; /* Nothing to enqueue */ + + acc100_dma_enqueue(q, enqueued_descs, &q_data->queue_stats); + + /* Update stats */ + q_data->queue_stats.enqueued_count += i; + q_data->queue_stats.enqueue_err_count += num - i; + + return i; +} + /* Check room in AQ for the enqueues batches into Qmgr */ static int32_t acc100_aq_avail(struct rte_bbdev_queue_data *q_data, uint16_t num_ops) @@ -3707,7 +3900,7 @@ acc100_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) - return acc100_enqueue_enc_tb(q_data, ops, num); + return acc100_enqueue_ldpc_enc_tb(q_data, ops, num); else return acc100_enqueue_ldpc_enc_cb(q_data, ops, num); } -- 2.37.1