From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7C8CA00C3; Mon, 15 Aug 2022 23:59:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C1A3B42BA5; Mon, 15 Aug 2022 23:57:47 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 47017415D7 for ; Mon, 15 Aug 2022 23:57:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600657; x=1692136657; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Vx/mjKrigloQ3GGPIiJYfs6bvGzINFNy41vTnu5s6Oo=; b=eNZtd6PVnmeol7gLoQFpis6qkzx6l0WBN7YRfSDQPoJCx9RitGYTNfLI mydviZV6matE0ICBe0sTL2ckGyaDJfkYtdLNrrdyzUvpxmoHOWCBdf76o 5VjrsGfIHJZsEjCnGwT9AjLIUPofzTkMzSGLafELskiBiQgkztOH7eCWB aTs40UC9e1aDHU0QqXMJm8PTB9w5cEG6shHtpHuLLBiwkop40Oa+Igyyl W2TjA+ijogA2RtcUpoZYD6Gls8QkLdupIr3lSPbQUrPgAQj9+W8i98Pcn wcP4wjtwPL/+Jea5UzzAqiT/Ji3hiHjEuAK3kY9ZwCDjj9lCpbydWWOBJ Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862720" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862720" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826064" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:36 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 15/33] baseband/acc100: configure PMON control registers Date: Mon, 15 Aug 2022 22:52:40 -0700 Message-Id: <20220816055258.107564-16-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable performance monitor control registers. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/acc100_pmd.h | 6 ++++++ drivers/baseband/acc100/rte_acc100_pmd.c | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h index 20157e5886..4a8d2e17ec 100644 --- a/drivers/baseband/acc100/acc100_pmd.h +++ b/drivers/baseband/acc100/acc100_pmd.h @@ -508,6 +508,8 @@ struct acc100_registry_addr { unsigned int depth_log1_offset; unsigned int qman_group_func; unsigned int ddr_range; + unsigned int pmon_ctrl_a; + unsigned int pmon_ctrl_b; }; /* Structure holding registry addresses for PF */ @@ -537,6 +539,8 @@ static const struct acc100_registry_addr pf_reg_addr = { .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf, .qman_group_func = HWPfQmgrGrpFunction0, .ddr_range = HWPfDmaVfDdrBaseRw, + .pmon_ctrl_a = HWPfPermonACntrlRegVf, + .pmon_ctrl_b = HWPfPermonBCntrlRegVf, }; /* Structure holding registry addresses for VF */ @@ -566,6 +570,8 @@ static const struct acc100_registry_addr vf_reg_addr = { .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf, .qman_group_func = HWVfQmgrGrpFunction0Vf, .ddr_range = HWVfDmaDdrBaseRangeRoVf, + .pmon_ctrl_a = HWVfPmACntrlRegVf, + .pmon_ctrl_b = HWVfPmBCntrlRegVf, }; /* Structure associated with each queue. */ diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index c85d28aa5c..b6c2c47091 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -653,6 +653,11 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) /* Read the populated cfg from ACC100 registers */ fetch_acc100_config(dev); + for (value = 0; value <= 2; value++) { + acc100_reg_write(d, reg_addr->pmon_ctrl_a, value); + acc100_reg_write(d, reg_addr->pmon_ctrl_b, value); + } + /* Release AXI from PF */ if (d->pf_device) acc100_reg_write(d, HWPfDmaAxiControl, 1); -- 2.37.1