From: Arek Kusztal <arkadiuszx.kusztal@intel.com>
To: dev@dpdk.org
Cc: gakhil@marvell.com, kai.ji@intel.com,
Arek Kusztal <arkadiuszx.kusztal@intel.com>
Subject: [PATCH] common/qat: read slice configuration
Date: Wed, 17 Aug 2022 09:10:44 +0100 [thread overview]
Message-ID: <20220817081044.80362-1-arkadiuszx.kusztal@intel.com> (raw)
Read slice configuration of QAT capabilities.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
drivers/common/qat/qat_device.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index db4b087d2b..d25a696c5e 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -368,6 +368,7 @@ static int qat_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
{ SYM_ENQ_THRESHOLD_NAME, 0 },
{ ASYM_ENQ_THRESHOLD_NAME, 0 },
{ COMP_ENQ_THRESHOLD_NAME, 0 },
+ { "DISABLE SLICE", 0},
{ NULL, 0 },
};
@@ -390,6 +391,17 @@ static int qat_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
return -ENODEV;
}
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
+ uint32_t capa = 0;
+ const uint32_t offset = 0x4c;
+
+ if (rte_pci_read_config(pci_dev, &capa, 4, offset) < 0) {
+ RTE_LOG(ERR, EAL,
+ "Cannot read slice configuration\n");
+ }
+ qat_dev_cmd_param[4].val |= (0x400 & capa) | (0x800 & capa);
+ }
+
sym_ret = qat_sym_dev_create(qat_pci_dev, qat_dev_cmd_param);
if (sym_ret == 0) {
num_pmds_created++;
--
2.17.1
reply other threads:[~2022-08-17 9:19 UTC|newest]
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