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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by BN8NAM11FT020.mail.protection.outlook.com (10.13.176.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5546.15 via Frontend Transport; Wed, 17 Aug 2022 14:14:14 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Wed, 17 Aug 2022 14:14:13 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 17 Aug 2022 07:14:11 -0700 From: Viacheslav Ovsiienko To: CC: , , , Subject: [PATCH] net/mlx5: fix the inline length exceeding descriptor limit Date: Wed, 17 Aug 2022 17:13:57 +0300 Message-ID: <20220817141357.7386-1-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ff9bc0be-17e8-4ac1-4e55-08da805ac3db X-MS-TrafficTypeDiagnostic: BL0PR12MB4996:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(396003)(376002)(346002)(39860400002)(136003)(40470700004)(46966006)(36840700001)(5660300002)(40460700003)(450100002)(478600001)(36756003)(40480700001)(356005)(55016003)(316002)(6916009)(6666004)(54906003)(41300700001)(70206006)(70586007)(2906002)(8936002)(4326008)(8676002)(1076003)(186003)(6286002)(2616005)(7696005)(86362001)(26005)(82310400005)(336012)(426003)(47076005)(16526019)(83380400001)(81166007)(82740400003)(36860700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2022 14:14:14.5813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff9bc0be-17e8-4ac1-4e55-08da805ac3db X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4996 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The hardware descriptor (WQE) length field is 6 bits wide and we have the native limitation for the overall descriptor length. To improve the PCIe bandwidth the packet data can be inline into descriptor. If PMD was configured to inline large amount of data it happened there was no enough space remaining in the descriptor to specify all the packet data segments and PMD rejected problematic packets. The patch tries to adjust the inline data length conservatively and allows to avoid error occurring. Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template") Fixes: e2259f93ef45 ("net/mlx5: fix Tx when inlining is impossible") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko Reviewed-by: Dmitry Kozlyuk --- drivers/net/mlx5/mlx5_tx.h | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h index 8e113e3778..59ebe95032 100644 --- a/drivers/net/mlx5/mlx5_tx.h +++ b/drivers/net/mlx5/mlx5_tx.h @@ -2078,8 +2078,24 @@ mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq, if (unlikely(loc->wqe_free < ((ds + 3) / 4))) return MLX5_TXCMP_CODE_EXIT; /* Check for maximal WQE size. */ - if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ds)) - return MLX5_TXCMP_CODE_ERROR; + if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ds)) { + /* Check if we can adjust the inline length. */ + if (unlikely(txq->inlen_mode)) { + ds = NB_SEGS(loc->mbuf) + 2 + + (txq->inlen_mode - + MLX5_ESEG_MIN_INLINE_SIZE + + MLX5_WSEG_SIZE + + MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE; + if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ds)) + return MLX5_TXCMP_CODE_ERROR; + } + /* We have lucky opportunity to adjust. */ + inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX - + MLX5_WSEG_SIZE * 2 - + MLX5_WSEG_SIZE * NB_SEGS(loc->mbuf) - + MLX5_WSEG_SIZE + + MLX5_ESEG_MIN_INLINE_SIZE); + } #ifdef MLX5_PMD_SOFT_COUNTERS /* Update sent data bytes/packets counters. */ txq->stats.obytes += dlen + vlan; -- 2.18.1