From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5A36A034C; Fri, 19 Aug 2022 20:38:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 99B8342BC5; Fri, 19 Aug 2022 20:36:35 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 57C0242B72 for ; Fri, 19 Aug 2022 20:36:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660934182; x=1692470182; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PDZNRizWbIZyXc60zbc0kiTL8AlCTOjv3SNJAW4gG7c=; b=fCOhT2tnCjvOe9Un67kRc873qTO1YjmbL75FIczqh0HdzcGeZ3JFgVL9 wpBWDxw2YPN/1dlx2519l/tP35IcUwoMqoN3hHfUWcedrz/4/wRBPZIp0 BcWlmmYaukOSs5Y77qwTg6l/53xZEydopmNxL22KFkLKqh/HJvG4N0RdJ tXAxwzXBBkvLYq90bjNLqCkywAG3+0cD8I/OfroJ1jtzNyR5YWjrKNbNX 9t6b8OQPvAmm47AS5Fv/HIID4DzVaL8qBs5of00BaOjNOktAOUDKLERcg Dm0c4Fdggi52u6hWVDmW1WqX+unYKcshWpP/fNI6zzbzVl1MMdvG/Fg/K A==; X-IronPort-AV: E=McAfee;i="6500,9779,10444"; a="319107287" X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="319107287" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 11:36:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="608296320" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga002.jf.intel.com with ESMTP; 19 Aug 2022 11:36:21 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v2 22/37] baseband/acc100: enforce additional check on FCW Date: Fri, 19 Aug 2022 19:31:42 -0700 Message-Id: <20220820023157.189047-23-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220820023157.189047-1-hernan.vargas@intel.com> References: <20220820023157.189047-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enforce additional check on Frame Control Word validity and add stronger alignment for decompression mode. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 40 ++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index ea850e2d7f..d67495ac52 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1508,6 +1508,20 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, fcw->hcin_offset = 0; fcw->hcin_size1 = 0; } + /* Enforce additional check on FCW validity */ + uint32_t max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, 64); + if ((fcw->hcin_size0 > max_hc_in) || + (fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) || + ((fcw->hcin_size0 > fcw->hcin_offset) && + (fcw->hcin_size1 != 0))) { + rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d", + fcw->hcin_size0, fcw->hcin_size1, + fcw->hcin_offset, + fcw->ncb, fcw->nfiller); + /* Disable HARQ input in that case to carry forward */ + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + fcw->hcin_en = 0; + } fcw->itmax = op->ldpc_dec.iter_max; fcw->itstop = check_bit(op->ldpc_dec.op_flags, @@ -1536,10 +1550,19 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, k0_p = (fcw->k0 > parity_offset) ? fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; ncb_p = fcw->ncb - op->ldpc_dec.n_filler; - l = k0_p + fcw->rm_e; + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX); harq_out_length = (uint16_t) fcw->hcin_size0; - harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p); - harq_out_length = (harq_out_length + 0x3F) & 0xFFC0; + harq_out_length = RTE_MAX(harq_out_length, l); + /* Stronger alignment when in compression mode */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 256); + /* Cannot exceed the pruned Ncb circular buffer */ + harq_out_length = RTE_MIN(harq_out_length, ncb_p); + /* Alignment on next 64B */ + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64); + /* Stronger alignment when in compression mode enforced again */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, 256); if ((k0_p > fcw->hcin_size0 + ACC100_HARQ_OFFSET_THRESHOLD) && harq_prun) { fcw->hcout_size0 = (uint16_t) fcw->hcin_size0; @@ -1550,6 +1573,13 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, fcw->hcout_size1 = 0; fcw->hcout_offset = 0; } + if (fcw->hcout_size0 == 0) { + rte_bbdev_log(ERR, " Invalid FCW : HCout %d", + fcw->hcout_size0); + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE; + fcw->hcout_en = 0; + } + harq_layout[harq_index].offset = fcw->hcout_offset; harq_layout[harq_index].size0 = fcw->hcout_size0; } else { @@ -1591,6 +1621,10 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, /* Disable HARQ input in that case to carry forward */ op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; } + if (unlikely(fcw->rm_e == 0)) { + rte_bbdev_log(WARNING, "Null E input provided"); + fcw->rm_e = 2; + } fcw->hcin_en = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); -- 2.37.1