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From: Hernan Vargas <hernan.vargas@intel.com>
To: dev@dpdk.org,
gakhil@marvell.com,
trix@redhat.com
Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com,
Hernan Vargas <hernan.vargas@intel.com>
Subject: [PATCH v2 27/37] baseband/acc100: store FCW from first CB descriptor
Date: Fri, 19 Aug 2022 19:31:47 -0700
Message-Id: <20220820023157.189047-28-hernan.vargas@intel.com>
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Store the descriptor from the first code block from a transport block.
Copy the LDPC FCW from the first descriptor into the rest of the CBs in
that TB.
Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 36455d5338..69de204293 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -3872,6 +3872,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op,
uint16_t total_enqueued_cbs, uint8_t cbs_in_tb)
{
union acc100_dma_desc *desc = NULL;
+ union acc100_dma_desc *desc_first = NULL;
int ret;
uint8_t r, c;
uint32_t in_offset, h_out_offset,
@@ -3890,6 +3891,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op,
uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs)
& q->sw_ring_wrap_mask);
desc = q->ring_addr + desc_idx;
+ desc_first = desc;
uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
@@ -3915,6 +3917,8 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op,
& q->sw_ring_wrap_mask);
desc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset;
desc->req.data_ptrs[0].blen = ACC100_FCW_LD_BLEN;
+ rte_memcpy(&desc->req.fcw_ld, &desc_first->req.fcw_ld,
+ ACC100_FCW_LD_BLEN);
ret = acc100_dma_desc_ld_fill(op, &desc->req, &input,
h_output, &in_offset, &h_out_offset,
&h_out_length,
--
2.37.1