From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C6494A0542; Mon, 29 Aug 2022 16:58:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6C84E4069D; Mon, 29 Aug 2022 16:58:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 519C44003C for ; Mon, 29 Aug 2022 16:58:41 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27T7fUpP010634 for ; Mon, 29 Aug 2022 07:58:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=hUo6Q0ABqHNIlh/XszHbgzS7dcMuAOsoSKZw5muyPxU=; b=cY4ANgwkPYs0xHceWlm3Od340giB255uJ9NdidV54AD45GWKpjUdyGoAUKxavZGNR7/Y ezlDiT7+LWGOSLByYn1eM7K/Fkjhl/mK3v8mE+WcIF40OvdLF9Ky9kUMHp62S0OEygDo mXuYBZHqLzrFdcEQ8B+mYXYqDKAZjwWrCmGDI8JPARTFJ9410a6DRHAXJTfvcMKvJ6Wt KUButaMrb7YW+qdgc+bkSMMaqZWq33/EiVpHoyUccUiJX1xc7vLbWlg9EhWaRxE89LDj HVEaoYrrTouTZH8ZE/Ev5jb5pTzkB92TFVHlkWd0DW4sdwvsDnvaG2EM76pxDPxR82WO Pw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3j7jsn7rbj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 29 Aug 2022 07:58:40 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 29 Aug 2022 07:58:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 29 Aug 2022 07:58:38 -0700 Received: from localhost.localdomain (unknown [10.28.36.158]) by maili.marvell.com (Postfix) with ESMTP id D6DD73F7072; Mon, 29 Aug 2022 07:58:36 -0700 (PDT) From: Rahul Bhansali To: , Pavan Nikhilesh , "Shijith Thotton" CC: , Rahul Bhansali Subject: [PATCH] event/cnxk: reassembly function callback assignment Date: Mon, 29 Aug 2022 20:28:21 +0530 Message-ID: <20220829145821.2514368-1-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: _8IptFoCSE6gUkOGEri0Tq_FH3ve4yR1 X-Proofpoint-GUID: _8IptFoCSE6gUkOGEri0Tq_FH3ve4yR1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-29_07,2022-08-25_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This add the support of reassembly functions callback assignment to eventdev dequeue and dequeue_burst. Fixes: c062f5726f61 ("net/cnxk: support IP reassembly") Signed-off-by: Rahul Bhansali --- drivers/event/cnxk/cn10k_eventdev.c | 232 ++++++++++++++---- .../cnxk/deq/cn10k/deq_0_15_tmo_seg_burst.c | 8 +- 2 files changed, 191 insertions(+), 49 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 5a0cab40a9..1db44323a5 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -389,69 +389,209 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev) #undef R }; + const event_dequeue_t sso_hws_reas_deq[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_reas_deq_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_burst_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_t sso_hws_reas_deq_tmo[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_tmo_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_reas_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_tmo_burst_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_t sso_hws_reas_deq_ca[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_ca_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_reas_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_ca_burst_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_t sso_hws_reas_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_tmo_ca_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_reas_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_tmo_ca_burst_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_t sso_hws_reas_deq_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_seg_##name, + + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_reas_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_seg_burst_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_t sso_hws_reas_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_tmo_seg_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_reas_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_tmo_seg_burst_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_t sso_hws_reas_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_ca_seg_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_reas_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_ca_seg_burst_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_t sso_hws_reas_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_tmo_ca_seg_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_reas_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn10k_sso_hws_reas_deq_tmo_ca_seg_burst_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + /* Tx modes */ - const event_tx_adapter_enqueue_t - sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = { + const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = { #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_##name, - NIX_TX_FASTPATH_MODES + NIX_TX_FASTPATH_MODES #undef T - }; + }; - const event_tx_adapter_enqueue_t - sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = { + const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = { #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_seg_##name, - NIX_TX_FASTPATH_MODES + NIX_TX_FASTPATH_MODES #undef T - }; + }; event_dev->enqueue = cn10k_sso_hws_enq; event_dev->enqueue_burst = cn10k_sso_hws_enq_burst; event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst; event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst; if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) { - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, - sso_hws_deq_seg); - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, - sso_hws_deq_seg_burst); - if (dev->is_timeout_deq) { - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, - sso_hws_deq_tmo_seg); + if (dev->rx_offloads & NIX_RX_REAS_F) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_reas_deq_seg); CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, - sso_hws_deq_tmo_seg_burst); - } - if (dev->is_ca_internal_port) { - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, - sso_hws_deq_ca_seg); - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, - sso_hws_deq_ca_seg_burst); - } - if (dev->is_timeout_deq && dev->is_ca_internal_port) { - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, - sso_hws_deq_tmo_ca_seg); + sso_hws_reas_deq_seg_burst); + if (dev->is_timeout_deq) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, + sso_hws_reas_deq_tmo_seg); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_reas_deq_tmo_seg_burst); + } + if (dev->is_ca_internal_port) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, + sso_hws_reas_deq_ca_seg); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_reas_deq_ca_seg_burst); + } + if (dev->is_timeout_deq && dev->is_ca_internal_port) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, + sso_hws_reas_deq_tmo_ca_seg); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_reas_deq_tmo_ca_seg_burst); + } + } else { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_seg); CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, - sso_hws_deq_tmo_ca_seg_burst); + sso_hws_deq_seg_burst); + + if (dev->is_timeout_deq) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, + sso_hws_deq_tmo_seg); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_deq_tmo_seg_burst); + } + if (dev->is_ca_internal_port) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_ca_seg); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_deq_ca_seg_burst); + } + if (dev->is_timeout_deq && dev->is_ca_internal_port) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, + sso_hws_deq_tmo_ca_seg); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_deq_tmo_ca_seg_burst); + } } } else { - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq); - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, - sso_hws_deq_burst); - if (dev->is_timeout_deq) { - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, - sso_hws_deq_tmo); - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, - sso_hws_deq_tmo_burst); - } - if (dev->is_ca_internal_port) { - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, - sso_hws_deq_ca); - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, - sso_hws_deq_ca_burst); - } - if (dev->is_timeout_deq && dev->is_ca_internal_port) { - CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, - sso_hws_deq_tmo_ca); + if (dev->rx_offloads & NIX_RX_REAS_F) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_reas_deq); CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, - sso_hws_deq_tmo_ca_burst); + sso_hws_reas_deq_burst); + + if (dev->is_timeout_deq) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, + sso_hws_reas_deq_tmo); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_reas_deq_tmo_burst); + } + if (dev->is_ca_internal_port) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, + sso_hws_reas_deq_ca); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_reas_deq_ca_burst); + } + if (dev->is_timeout_deq && dev->is_ca_internal_port) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, + sso_hws_reas_deq_tmo_ca); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_reas_deq_tmo_ca_burst); + } + } else { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, sso_hws_deq_burst); + + if (dev->is_timeout_deq) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_tmo); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_deq_tmo_burst); + } + if (dev->is_ca_internal_port) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_ca); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_deq_ca_burst); + } + if (dev->is_timeout_deq && dev->is_ca_internal_port) { + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_tmo_ca); + CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_deq_tmo_ca_burst); + } } } event_dev->ca_enqueue = cn10k_sso_hws_ca_enq; diff --git a/drivers/event/cnxk/deq/cn10k/deq_0_15_tmo_seg_burst.c b/drivers/event/cnxk/deq/cn10k/deq_0_15_tmo_seg_burst.c index 2dff8795c8..9af8d6e128 100644 --- a/drivers/event/cnxk/deq/cn10k/deq_0_15_tmo_seg_burst.c +++ b/drivers/event/cnxk/deq/cn10k/deq_0_15_tmo_seg_burst.c @@ -6,9 +6,11 @@ #include "cnxk_eventdev.h" #include "cnxk_worker.h" -#define R(name, flags) \ - SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_seg_burst_##name, \ - cn10k_sso_hws_reas_deq_tmo_seg_##name, flags) +#define R(name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_deq_tmo_seg_burst_##name, \ + cn10k_sso_hws_deq_tmo_seg_##name, flags) \ + SSO_CMN_DEQ_BURST(cn10k_sso_hws_reas_deq_tmo_seg_burst_##name, \ + cn10k_sso_hws_reas_deq_tmo_seg_##name, flags | NIX_RX_REAS_F) NIX_RX_FASTPATH_MODES_0_15 #undef R -- 2.25.1