From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0AA26A0558; Mon, 5 Sep 2022 15:33:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3760842836; Mon, 5 Sep 2022 15:33:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id BA44A42B87 for ; Mon, 5 Sep 2022 15:33:24 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 285CToUk031672 for ; Mon, 5 Sep 2022 06:33:24 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=phd/9kVFjCDQWqYH60p1MBPrZdNdc2dsI8dxzKcYfJo=; b=UHlUIAJTeJU9Uh+5D2siB5TtaGkZ94AnaUIKSlP8pAXYrMFC/ENIED0bZrLMMbyvFOpR q6Lt+40/ICBJOySFc03NH+A7DKrU4X7XuKqtZmEzzlpVTJqpkiF7Mc4osVE8BF4kTVU/ F9kfdJOA9C1uV2EHRGUQmiDkIgqqNU5hB1OKH2eYbuOrRI185NvaftrZBnfSBXEfjT+F kzQPPonkZ2bA6OGdX6saTFxEaaq5cj4Bti1oWQcOIr8F+3nQ4zUequWF8FOkGRmZ8EI6 z26R4kdIcpwIQE+4KnvRgk8IKcJpP0lWaCG4eAqbWQOk2Q47iM1WCeSOvFS0NZ/U6rx8 dw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3jc6epnggq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 05 Sep 2022 06:33:24 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 5 Sep 2022 06:33:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 5 Sep 2022 06:33:21 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 00B615E6870; Mon, 5 Sep 2022 06:33:19 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v2 17/31] common/cnxk: updated shaper profile with red algorithm Date: Mon, 5 Sep 2022 19:02:14 +0530 Message-ID: <20220905133228.818616-17-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220905133228.818616-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> <20220905133228.818616-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: nzmHF1VLXTbrxbsaJQ6wiaHpnqktm_t3 X-Proofpoint-GUID: nzmHF1VLXTbrxbsaJQ6wiaHpnqktm_t3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-09-05_09,2022-09-05_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Updated shaper profile with user configurable RED algorithm. This helps in configuring a TM node in red drop mode vs stall mode. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_tm_utils.c | 7 +++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 77e4d2919b..b17623076c 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -572,6 +572,7 @@ struct roc_nix_tm_shaper_profile { int32_t pkt_len_adj; bool pkt_mode; int8_t accuracy; + uint8_t red_algo; /* Function to free this memory */ void (*free_fn)(void *profile); }; diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index b9b605f8b1..193f9df5ff 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -1236,11 +1236,14 @@ roc_nix_tm_shaper_default_red_algo(struct roc_nix_tm_node *node, struct nix_tm_shaper_profile *profile; struct nix_tm_shaper_data cir, pir; + if (!roc_prof) + return; + profile = (struct nix_tm_shaper_profile *)roc_prof->reserved; - tm_node->red_algo = NIX_REDALG_STD; + tm_node->red_algo = roc_prof->red_algo; /* C0 doesn't support STALL when both PIR & CIR are enabled */ - if (profile && roc_model_is_cn96_cx()) { + if (roc_model_is_cn96_cx()) { nix_tm_shaper_conf_get(profile, &cir, &pir); if (pir.rate && cir.rate) -- 2.25.1