From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9CE0BA0558; Mon, 5 Sep 2022 15:34:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 08C2642802; Mon, 5 Sep 2022 15:33:29 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0A32142B8B for ; Mon, 5 Sep 2022 15:33:26 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 285CP7LD019930 for ; Mon, 5 Sep 2022 06:33:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=9vVVezbZsw+9qOy+sDTs5KS+uc4dLeuJXD8TnoioISw=; b=ZeCPx4A1aEFOpl2zZTdNROQKvj5+GjpDX9wi38PTnseOiwQ3Ibjq9ndzuj/hXYWrdpt3 GpGlsDSGMuCYtT6JVJy/Ud84Qc5nGY7qDQd5ROPLcbtQ0dWX16PzwV3YMkGne6Wyfe00 DpuNXaGP20mJvFBK0um0xP5WyRVnehG6ttzpDXWKORggDrmk968ya93IRbR+T3JF3CVj Yzgza4ccaz949QbD4q46MBjYoizTzOwjo5MNb4Wzp/FD/sdwy7G25JcIAnPrpBm7m4pK F1LAmyYrOcUTIuDYj3BqvYuqcDaUrar4Zo8d9RfZ+AUJLzg8zUsgwEbVs8MuIG08YTzV Sg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3jc49qdv4s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 05 Sep 2022 06:33:26 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 5 Sep 2022 06:33:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 5 Sep 2022 06:33:24 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 81A485E686D; Mon, 5 Sep 2022 06:33:22 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Harman Kalra Subject: [PATCH v2 18/31] common/cnxk: add 98xx A1 platform Date: Mon, 5 Sep 2022 19:02:15 +0530 Message-ID: <20220905133228.818616-18-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220905133228.818616-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> <20220905133228.818616-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: gJXclO_Nu5IJm9cGinOSeTkun2DNeDRB X-Proofpoint-ORIG-GUID: gJXclO_Nu5IJm9cGinOSeTkun2DNeDRB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-09-05_09,2022-09-05_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Harman Kalra Adding support for 98xx A1 pass chip. Signed-off-by: Harman Kalra --- drivers/common/cnxk/roc_model.c | 1 + drivers/common/cnxk/roc_model.h | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c index bdbd9a96b2..04338311ec 100644 --- a/drivers/common/cnxk/roc_model.c +++ b/drivers/common/cnxk/roc_model.c @@ -65,6 +65,7 @@ static const struct model_db { {VENDOR_ARM, PART_103xx, 0, 0, ROC_MODEL_CN103xx_A0, "cn10kb_a0"}, {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"}, {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"}, + {VENDOR_CAVIUM, PART_98xx, 0, 1, ROC_MODEL_CN98xx_A1, "cn98xx_a1"}, {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"}, {VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"}, {VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"}, diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index d231d44b60..57a8af06fc 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -21,6 +21,7 @@ struct roc_model { #define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14) #define ROC_MODEL_CNF95xxN_B0 BIT_ULL(15) #define ROC_MODEL_CN98xx_A0 BIT_ULL(16) +#define ROC_MODEL_CN98xx_A1 BIT_ULL(17) #define ROC_MODEL_CN106xx_A0 BIT_ULL(20) #define ROC_MODEL_CNF105xx_A0 BIT_ULL(21) #define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22) @@ -38,10 +39,11 @@ struct roc_model { } __plt_cache_aligned; #define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0) +#define ROC_MODEL_CN98xx_Ax (ROC_MODEL_CN98xx_A0 | ROC_MODEL_CN98xx_A1) #define ROC_MODEL_CN9K \ (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \ ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \ - ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \ + ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_Ax | \ ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0) #define ROC_MODEL_CNF9K \ (ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 | \ @@ -110,10 +112,22 @@ roc_model_is_cn10k(void) static inline uint64_t roc_model_is_cn98xx(void) +{ + return (roc_model->flag & ROC_MODEL_CN98xx_Ax); +} + +static inline uint64_t +roc_model_is_cn98xx_a0(void) { return (roc_model->flag & ROC_MODEL_CN98xx_A0); } +static inline uint64_t +roc_model_is_cn98xx_a1(void) +{ + return (roc_model->flag & ROC_MODEL_CN98xx_A1); +} + static inline uint64_t roc_model_is_cn96_a0(void) { -- 2.25.1