* [PATCH 1/5] test/crypto: add cryptodev_uadk_autotest
2022-09-11 5:23 [PATCH 0/5] crypto/uadk: introduce uadk crypto driver Zhangfei Gao
@ 2022-09-11 5:23 ` Zhangfei Gao
2022-09-11 5:23 ` [PATCH 2/5] crypto/uadk: introduce uadk crypto driver Zhangfei Gao
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Zhangfei Gao @ 2022-09-11 5:23 UTC (permalink / raw)
To: Akhil Goyal, Declan Doherty, Fan Zhang, Ashish Gupta, Ray Kinsella
Cc: dev, acc, Zhangfei Gao
Example:
sudo dpdk-test --vdev=crypto_uadk --log-level=6
RTE>>cryptodev_uadk_autotest
RTE>>quit
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
app/test/test_cryptodev.c | 7 +++++++
app/test/test_cryptodev.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 6ee4480399..7541cffd36 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -16580,6 +16580,12 @@ test_cryptodev_qat(void)
return run_cryptodev_testsuite(RTE_STR(CRYPTODEV_NAME_QAT_SYM_PMD));
}
+static int
+test_cryptodev_uadk(void)
+{
+ return run_cryptodev_testsuite(RTE_STR(CRYPTODEV_NAME_UADK_PMD));
+}
+
static int
test_cryptodev_virtio(void)
{
@@ -16923,6 +16929,7 @@ REGISTER_TEST_COMMAND(cryptodev_sw_mvsam_autotest, test_cryptodev_mrvl);
REGISTER_TEST_COMMAND(cryptodev_dpaa2_sec_autotest, test_cryptodev_dpaa2_sec);
REGISTER_TEST_COMMAND(cryptodev_dpaa_sec_autotest, test_cryptodev_dpaa_sec);
REGISTER_TEST_COMMAND(cryptodev_ccp_autotest, test_cryptodev_ccp);
+REGISTER_TEST_COMMAND(cryptodev_uadk_autotest, test_cryptodev_uadk);
REGISTER_TEST_COMMAND(cryptodev_virtio_autotest, test_cryptodev_virtio);
REGISTER_TEST_COMMAND(cryptodev_octeontx_autotest, test_cryptodev_octeontx);
REGISTER_TEST_COMMAND(cryptodev_caam_jr_autotest, test_cryptodev_caam_jr);
diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h
index 29a7d4db2b..abd795f54a 100644
--- a/app/test/test_cryptodev.h
+++ b/app/test/test_cryptodev.h
@@ -74,6 +74,7 @@
#define CRYPTODEV_NAME_CN9K_PMD crypto_cn9k
#define CRYPTODEV_NAME_CN10K_PMD crypto_cn10k
#define CRYPTODEV_NAME_MLX5_PMD crypto_mlx5
+#define CRYPTODEV_NAME_UADK_PMD crypto_uadk
enum cryptodev_api_test_type {
--
2.36.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 2/5] crypto/uadk: introduce uadk crypto driver
2022-09-11 5:23 [PATCH 0/5] crypto/uadk: introduce uadk crypto driver Zhangfei Gao
2022-09-11 5:23 ` [PATCH 1/5] test/crypto: add cryptodev_uadk_autotest Zhangfei Gao
@ 2022-09-11 5:23 ` Zhangfei Gao
2022-09-11 5:23 ` [PATCH 3/5] crypto/uadk: support cipher algorithms Zhangfei Gao
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Zhangfei Gao @ 2022-09-11 5:23 UTC (permalink / raw)
To: Akhil Goyal, Declan Doherty, Fan Zhang, Ashish Gupta, Ray Kinsella
Cc: dev, acc, Zhangfei Gao
Introduce a new crypto PMD for UADK, which relies on UADK library [1].
UADK is a framework for user applications to access hardware accelerators.
UADK relies on IOMMU SVA (Shared Virtual Address) feature, which share
the same page table between IOMMU and MMU.
Thereby user application can directly use virtual address for device dma,
which enhances the performance as well as easy usability.
Currently supported platforms:
HiSilicon kunpeng920 & kunpeng930.
This patch add basic framework.
[1] https://github.com/Linaro/uadk
Test:
sudo dpdk-test --vdev=crypto_uadk (--log-level=6)
RTE>>cryptodev_uadk_autotest
RTE>>quit
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
drivers/crypto/meson.build | 1 +
drivers/crypto/uadk/meson.build | 36 +++
drivers/crypto/uadk/uadk_crypto_pmd.c | 450 ++++++++++++++++++++++++++
drivers/crypto/uadk/version.map | 3 +
4 files changed, 490 insertions(+)
create mode 100644 drivers/crypto/uadk/meson.build
create mode 100644 drivers/crypto/uadk/uadk_crypto_pmd.c
create mode 100644 drivers/crypto/uadk/version.map
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index 147b8cf633..ee5377deff 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -18,6 +18,7 @@ drivers = [
'octeontx',
'openssl',
'scheduler',
+ 'uadk',
'virtio',
]
diff --git a/drivers/crypto/uadk/meson.build b/drivers/crypto/uadk/meson.build
new file mode 100644
index 0000000000..a67c6c7ca5
--- /dev/null
+++ b/drivers/crypto/uadk/meson.build
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2022-2023 Huawei Technologies Co.,Ltd. All rights reserved.
+# Copyright 2022-2023 Linaro ltd.
+
+if not is_linux
+ build = false
+ reason = 'only supported on Linux'
+ subdir_done()
+endif
+
+if arch_subdir != 'arm' or not dpdk_conf.get('RTE_ARCH_64')
+ build = false
+ reason = 'only supported on aarch64'
+ subdir_done()
+endif
+
+sources = files(
+ 'uadk_crypto_pmd.c',
+)
+
+deps += 'bus_vdev'
+dep = cc.find_library('libwd_crypto', dirs: ['/usr/local/lib'], required: false)
+if not dep.found()
+ build = false
+ reason = 'missing dependency, "libwd_crypto"'
+else
+ ext_deps += dep
+endif
+
+dep = cc.find_library('libwd', dirs: ['/usr/local/lib'], required: false)
+if not dep.found()
+ build = false
+ reason = 'missing dependency, "libwd"'
+else
+ ext_deps += dep
+endif
diff --git a/drivers/crypto/uadk/uadk_crypto_pmd.c b/drivers/crypto/uadk/uadk_crypto_pmd.c
new file mode 100644
index 0000000000..486aeab08b
--- /dev/null
+++ b/drivers/crypto/uadk/uadk_crypto_pmd.c
@@ -0,0 +1,450 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2022-2023 Huawei Technologies Co.,Ltd. All rights reserved.
+ * Copyright 2022-2023 Linaro ltd.
+ */
+
+#include <cryptodev_pmd.h>
+#include <rte_bus_vdev.h>
+#include <rte_comp.h>
+#include <uadk/wd_cipher.h>
+#include <uadk/wd_digest.h>
+#include <uadk/wd_sched.h>
+
+/* Maximum length for digest (SHA-512 needs 64 bytes) */
+#define DIGEST_LENGTH_MAX 64
+
+struct uadk_qp {
+ struct rte_ring *processed_pkts;
+ /* Ring for placing process packets */
+ struct rte_cryptodev_stats qp_stats;
+ /* Queue pair statistics */
+ uint16_t id;
+ /* Queue Pair Identifier */
+ char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+ /* Unique Queue Pair Name */
+ uint8_t temp_digest[DIGEST_LENGTH_MAX];
+ /* Buffer used to store the digest generated
+ * by the driver when verifying a digest provided
+ * by the user (using authentication verify operation)
+ */
+} __rte_cache_aligned;
+
+enum uadk_chain_order {
+ UADK_CHAIN_NOT_SUPPORTED
+};
+
+struct uadk_crypto_session {
+ enum uadk_chain_order chain_order;
+} __rte_cache_aligned;
+
+enum uadk_supported_platform {
+ UADK_KUNPENG920,
+ UADK_KUNPENG930,
+};
+
+struct uadk_crypto_priv {
+ enum uadk_supported_platform platform;
+} __rte_cache_aligned;
+
+static uint8_t uadk_cryptodev_driver_id;
+
+RTE_LOG_REGISTER_DEFAULT(uadk_crypto_logtype, INFO);
+
+#define UADK_LOG(level, fmt, ...) \
+ rte_log(RTE_LOG_ ## level, uadk_crypto_logtype, \
+ "%s() line %u: " fmt "\n", __func__, __LINE__, \
+ ## __VA_ARGS__)
+
+static const struct rte_cryptodev_capabilities uadk_crypto_920_capabilities[] = {
+ /* End of symmetric capabilities */
+ RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+/* Configure device */
+static int
+uadk_crypto_pmd_config(struct rte_cryptodev *dev __rte_unused,
+ struct rte_cryptodev_config *config __rte_unused)
+{
+ return 0;
+}
+
+/* Start device */
+static int
+uadk_crypto_pmd_start(struct rte_cryptodev *dev __rte_unused)
+{
+ return 0;
+}
+
+/* Stop device */
+static void
+uadk_crypto_pmd_stop(struct rte_cryptodev *dev __rte_unused)
+{
+}
+
+/* Close device */
+static int
+uadk_crypto_pmd_close(struct rte_cryptodev *dev __rte_unused)
+{
+ return 0;
+}
+
+/* Get device statistics */
+static void
+uadk_crypto_pmd_stats_get(struct rte_cryptodev *dev,
+ struct rte_cryptodev_stats *stats)
+{
+ int qp_id;
+
+ for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
+ struct uadk_qp *qp = dev->data->queue_pairs[qp_id];
+
+ stats->enqueued_count += qp->qp_stats.enqueued_count;
+ stats->dequeued_count += qp->qp_stats.dequeued_count;
+ stats->enqueue_err_count += qp->qp_stats.enqueue_err_count;
+ stats->dequeue_err_count += qp->qp_stats.dequeue_err_count;
+ }
+}
+
+/* Reset device statistics */
+static void
+uadk_crypto_pmd_stats_reset(struct rte_cryptodev *dev __rte_unused)
+{
+ int qp_id;
+
+ for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
+ struct uadk_qp *qp = dev->data->queue_pairs[qp_id];
+
+ memset(&qp->qp_stats, 0, sizeof(qp->qp_stats));
+ }
+}
+
+/* Get device info */
+static void
+uadk_crypto_pmd_info_get(struct rte_cryptodev *dev,
+ struct rte_cryptodev_info *dev_info)
+{
+ struct uadk_crypto_priv *priv = dev->data->dev_private;
+
+ if (dev_info != NULL) {
+ dev_info->driver_id = dev->driver_id;
+ dev_info->driver_name = dev->device->driver->name;
+ dev_info->max_nb_queue_pairs = 128;
+ /* No limit of number of sessions */
+ dev_info->sym.max_nb_sessions = 0;
+ dev_info->feature_flags = dev->feature_flags;
+
+ if (priv->platform == UADK_KUNPENG920)
+ dev_info->capabilities = uadk_crypto_920_capabilities;
+ }
+}
+
+/* Release queue pair */
+static int
+uadk_crypto_pmd_qp_release(struct rte_cryptodev *dev, uint16_t qp_id)
+{
+ struct uadk_qp *qp = dev->data->queue_pairs[qp_id];
+
+ if (qp) {
+ rte_ring_free(qp->processed_pkts);
+ rte_free(qp);
+ dev->data->queue_pairs[qp_id] = NULL;
+ }
+
+ return 0;
+}
+
+/* set a unique name for the queue pair based on its name, dev_id and qp_id */
+static int
+uadk_pmd_qp_set_unique_name(struct rte_cryptodev *dev,
+ struct uadk_qp *qp)
+{
+ unsigned int n = snprintf(qp->name, sizeof(qp->name),
+ "uadk_crypto_pmd_%u_qp_%u",
+ dev->data->dev_id, qp->id);
+
+ if (n >= sizeof(qp->name))
+ return -EINVAL;
+
+ return 0;
+}
+
+/* Create a ring to place process packets on */
+static struct rte_ring *
+uadk_pmd_qp_create_processed_pkts_ring(struct uadk_qp *qp,
+ unsigned int ring_size, int socket_id)
+{
+ struct rte_ring *r = qp->processed_pkts;
+
+ if (r) {
+ if (rte_ring_get_size(r) >= ring_size) {
+ UADK_LOG(INFO, "Reusing existing ring %s for processed packets",
+ qp->name);
+ return r;
+ }
+
+ UADK_LOG(ERR, "Unable to reuse existing ring %s for processed packets",
+ qp->name);
+ return NULL;
+ }
+
+ return rte_ring_create(qp->name, ring_size, socket_id,
+ RING_F_EXACT_SZ);
+}
+
+static int
+uadk_crypto_pmd_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
+ const struct rte_cryptodev_qp_conf *qp_conf,
+ int socket_id)
+{
+ struct uadk_qp *qp;
+
+ /* Free memory prior to re-allocation if needed. */
+ if (dev->data->queue_pairs[qp_id] != NULL)
+ uadk_crypto_pmd_qp_release(dev, qp_id);
+
+ /* Allocate the queue pair data structure. */
+ qp = rte_zmalloc_socket("uadk PMD Queue Pair", sizeof(*qp),
+ RTE_CACHE_LINE_SIZE, socket_id);
+ if (qp == NULL)
+ return (-ENOMEM);
+
+ qp->id = qp_id;
+ dev->data->queue_pairs[qp_id] = qp;
+
+ if (uadk_pmd_qp_set_unique_name(dev, qp))
+ goto qp_setup_cleanup;
+
+ qp->processed_pkts = uadk_pmd_qp_create_processed_pkts_ring(qp,
+ qp_conf->nb_descriptors, socket_id);
+ if (qp->processed_pkts == NULL)
+ goto qp_setup_cleanup;
+
+ memset(&qp->qp_stats, 0, sizeof(qp->qp_stats));
+
+ return 0;
+
+qp_setup_cleanup:
+ if (qp) {
+ rte_free(qp);
+ qp = NULL;
+ }
+ return -EINVAL;
+}
+
+static unsigned int
+uadk_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
+{
+ return sizeof(struct uadk_crypto_session);
+}
+
+static enum uadk_chain_order
+uadk_get_chain_order(const struct rte_crypto_sym_xform *xform __rte_unused)
+{
+ enum uadk_chain_order res = UADK_CHAIN_NOT_SUPPORTED;
+
+ return res;
+}
+
+static int
+uadk_crypto_sym_session_configure(struct rte_cryptodev *dev,
+ struct rte_crypto_sym_xform *xform,
+ struct rte_cryptodev_sym_session *session,
+ struct rte_mempool *mp)
+{
+ struct uadk_crypto_session *sess;
+ int ret;
+
+ ret = rte_mempool_get(mp, (void *)&sess);
+ if (ret != 0) {
+ UADK_LOG(ERR, "Failed to get session %p private data from mempool",
+ sess);
+ return -ENOMEM;
+ }
+
+ sess->chain_order = uadk_get_chain_order(xform);
+ switch (sess->chain_order) {
+ default:
+ ret = -ENOTSUP;
+ goto err;
+ }
+
+ set_sym_session_private_data(session, dev->driver_id, sess);
+
+ return 0;
+err:
+ rte_mempool_put(mp, sess);
+ return ret;
+}
+
+static void
+uadk_crypto_sym_session_clear(struct rte_cryptodev *dev,
+ struct rte_cryptodev_sym_session *sess)
+{
+ struct uadk_crypto_session *priv_sess =
+ get_sym_session_private_data(sess, dev->driver_id);
+
+ if (unlikely(priv_sess == NULL)) {
+ UADK_LOG(ERR, "Failed to get session %p private data.", priv_sess);
+ return;
+ }
+
+ set_sym_session_private_data(sess, dev->driver_id, NULL);
+ rte_mempool_put(rte_mempool_from_obj(priv_sess), priv_sess);
+}
+
+static struct rte_cryptodev_ops uadk_crypto_pmd_ops = {
+ .dev_configure = uadk_crypto_pmd_config,
+ .dev_start = uadk_crypto_pmd_start,
+ .dev_stop = uadk_crypto_pmd_stop,
+ .dev_close = uadk_crypto_pmd_close,
+ .stats_get = uadk_crypto_pmd_stats_get,
+ .stats_reset = uadk_crypto_pmd_stats_reset,
+ .dev_infos_get = uadk_crypto_pmd_info_get,
+ .queue_pair_setup = uadk_crypto_pmd_qp_setup,
+ .queue_pair_release = uadk_crypto_pmd_qp_release,
+ .sym_session_get_size = uadk_crypto_sym_session_get_size,
+ .sym_session_configure = uadk_crypto_sym_session_configure,
+ .sym_session_clear = uadk_crypto_sym_session_clear,
+};
+
+static uint16_t
+uadk_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
+ uint16_t nb_ops)
+{
+ struct uadk_qp *qp = queue_pair;
+ struct uadk_crypto_session *sess = NULL;
+ struct rte_crypto_op *op;
+ uint16_t enqd = 0;
+ int i, ret;
+
+ for (i = 0; i < nb_ops; i++) {
+ op = ops[i];
+ op->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;
+
+ if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
+ if (likely(op->sym->session != NULL))
+ sess = (struct uadk_crypto_session *)
+ get_sym_session_private_data(
+ op->sym->session,
+ uadk_cryptodev_driver_id);
+ }
+
+ switch (sess->chain_order) {
+ default:
+ op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ break;
+ }
+
+ if (op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED)
+ op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+
+ if (op->status != RTE_CRYPTO_OP_STATUS_ERROR) {
+ ret = rte_ring_enqueue(qp->processed_pkts, (void *)op);
+ if (ret < 0)
+ goto enqueue_err;
+ qp->qp_stats.enqueued_count++;
+ enqd++;
+ } else {
+ /* increment count if failed to enqueue op */
+ qp->qp_stats.enqueue_err_count++;
+ }
+ }
+
+ return enqd;
+
+enqueue_err:
+ qp->qp_stats.enqueue_err_count++;
+ return enqd;
+}
+
+static uint16_t
+uadk_crypto_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops,
+ uint16_t nb_ops)
+{
+ struct uadk_qp *qp = queue_pair;
+ unsigned int nb_dequeued;
+
+ nb_dequeued = rte_ring_dequeue_burst(qp->processed_pkts,
+ (void **)ops, nb_ops, NULL);
+ qp->qp_stats.dequeued_count += nb_dequeued;
+
+ return nb_dequeued;
+}
+
+static int
+uadk_cryptodev_probe(struct rte_vdev_device *vdev)
+{
+ struct rte_cryptodev_pmd_init_params init_params = {
+ .name = "",
+ .private_data_size = sizeof(struct uadk_crypto_priv),
+ .max_nb_queue_pairs =
+ RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS,
+ };
+ enum uadk_supported_platform platform = UADK_KUNPENG920;
+ struct uadk_crypto_priv *priv;
+ struct rte_cryptodev *dev;
+ struct uacce_dev *udev;
+ const char *name;
+
+ udev = wd_get_accel_dev("cipher");
+ if (!udev)
+ return -ENODEV;
+
+ if (!strcmp(udev->api, "hisi_qm_v2"))
+ platform = UADK_KUNPENG920;
+
+ free(udev);
+
+ name = rte_vdev_device_name(vdev);
+ if (name == NULL)
+ return -EINVAL;
+
+ dev = rte_cryptodev_pmd_create(name, &vdev->device, &init_params);
+ if (dev == NULL) {
+ UADK_LOG(ERR, "driver %s: create failed", init_params.name);
+ return -ENODEV;
+ }
+
+ dev->dev_ops = &uadk_crypto_pmd_ops;
+ dev->driver_id = uadk_cryptodev_driver_id;
+ dev->dequeue_burst = uadk_crypto_dequeue_burst;
+ dev->enqueue_burst = uadk_crypto_enqueue_burst;
+ dev->feature_flags = RTE_CRYPTODEV_FF_HW_ACCELERATED |
+ RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
+ RTE_CRYPTODEV_FF_SYM_SESSIONLESS;
+ priv = dev->data->dev_private;
+ priv->platform = platform;
+
+ rte_cryptodev_pmd_probing_finish(dev);
+
+ return 0;
+}
+
+static int
+uadk_cryptodev_remove(struct rte_vdev_device *vdev)
+{
+ struct rte_cryptodev *cryptodev;
+ const char *name;
+
+ name = rte_vdev_device_name(vdev);
+ if (name == NULL)
+ return -EINVAL;
+
+ cryptodev = rte_cryptodev_pmd_get_named_dev(name);
+ if (cryptodev == NULL)
+ return -ENODEV;
+
+ return rte_cryptodev_pmd_destroy(cryptodev);
+}
+
+static struct rte_vdev_driver uadk_crypto_pmd = {
+ .probe = uadk_cryptodev_probe,
+ .remove = uadk_cryptodev_remove,
+};
+
+static struct cryptodev_driver uadk_crypto_drv;
+
+#define UADK_CRYPTO_DRIVER_NAME crypto_uadk
+RTE_PMD_REGISTER_VDEV(UADK_CRYPTO_DRIVER_NAME, uadk_crypto_pmd);
+RTE_PMD_REGISTER_CRYPTO_DRIVER(uadk_crypto_drv, uadk_crypto_pmd.driver,
+ uadk_cryptodev_driver_id);
diff --git a/drivers/crypto/uadk/version.map b/drivers/crypto/uadk/version.map
new file mode 100644
index 0000000000..c2e0723b4c
--- /dev/null
+++ b/drivers/crypto/uadk/version.map
@@ -0,0 +1,3 @@
+DPDK_22 {
+ local: *;
+};
--
2.36.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 3/5] crypto/uadk: support cipher algorithms
2022-09-11 5:23 [PATCH 0/5] crypto/uadk: introduce uadk crypto driver Zhangfei Gao
2022-09-11 5:23 ` [PATCH 1/5] test/crypto: add cryptodev_uadk_autotest Zhangfei Gao
2022-09-11 5:23 ` [PATCH 2/5] crypto/uadk: introduce uadk crypto driver Zhangfei Gao
@ 2022-09-11 5:23 ` Zhangfei Gao
2022-09-11 5:23 ` [PATCH 4/5] crypto/uadk: support auth algorithms Zhangfei Gao
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Zhangfei Gao @ 2022-09-11 5:23 UTC (permalink / raw)
To: Akhil Goyal, Declan Doherty, Fan Zhang, Ashish Gupta, Ray Kinsella
Cc: dev, acc, Zhangfei Gao
Cipher algorithms:
* ``RTE_CRYPTO_CIPHER_AES_ECB``
* ``RTE_CRYPTO_CIPHER_AES_CBC``
* ``RTE_CRYPTO_CIPHER_AES_XTS``
* ``RTE_CRYPTO_CIPHER_DES_CBC``
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
drivers/crypto/uadk/uadk_crypto_pmd.c | 254 +++++++++++++++++++++++++-
1 file changed, 252 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/uadk/uadk_crypto_pmd.c b/drivers/crypto/uadk/uadk_crypto_pmd.c
index 486aeab08b..7ca3e3ecd8 100644
--- a/drivers/crypto/uadk/uadk_crypto_pmd.c
+++ b/drivers/crypto/uadk/uadk_crypto_pmd.c
@@ -30,11 +30,26 @@ struct uadk_qp {
} __rte_cache_aligned;
enum uadk_chain_order {
+ UADK_CHAIN_ONLY_CIPHER,
UADK_CHAIN_NOT_SUPPORTED
};
struct uadk_crypto_session {
+ handle_t handle_cipher;
enum uadk_chain_order chain_order;
+
+ /* IV parameters */
+ struct {
+ uint16_t length;
+ uint16_t offset;
+ } iv;
+
+ /* Cipher Parameters */
+ struct {
+ enum rte_crypto_cipher_operation direction;
+ /* cipher operation direction */
+ struct wd_cipher_req req;
+ } cipher;
} __rte_cache_aligned;
enum uadk_supported_platform {
@@ -43,6 +58,7 @@ enum uadk_supported_platform {
};
struct uadk_crypto_priv {
+ bool env_cipher_init;
enum uadk_supported_platform platform;
} __rte_cache_aligned;
@@ -56,6 +72,86 @@ RTE_LOG_REGISTER_DEFAULT(uadk_crypto_logtype, INFO);
## __VA_ARGS__)
static const struct rte_cryptodev_capabilities uadk_crypto_920_capabilities[] = {
+ { /* AES ECB */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_ECB,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .iv_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* AES CBC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_CBC,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* AES XTS */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_XTS,
+ .block_size = 1,
+ .key_size = {
+ .min = 32,
+ .max = 64,
+ .increment = 32
+ },
+ .iv_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* DES CBC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_DES_CBC,
+ .block_size = 8,
+ .key_size = {
+ .min = 8,
+ .max = 8,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 8,
+ .max = 8,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
/* End of symmetric capabilities */
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
@@ -83,8 +179,15 @@ uadk_crypto_pmd_stop(struct rte_cryptodev *dev __rte_unused)
/* Close device */
static int
-uadk_crypto_pmd_close(struct rte_cryptodev *dev __rte_unused)
+uadk_crypto_pmd_close(struct rte_cryptodev *dev)
{
+ struct uadk_crypto_priv *priv = dev->data->dev_private;
+
+ if (priv->env_cipher_init) {
+ wd_cipher_env_uninit();
+ priv->env_cipher_init = false;
+ }
+
return 0;
}
@@ -238,19 +341,107 @@ uadk_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
}
static enum uadk_chain_order
-uadk_get_chain_order(const struct rte_crypto_sym_xform *xform __rte_unused)
+uadk_get_chain_order(const struct rte_crypto_sym_xform *xform)
{
enum uadk_chain_order res = UADK_CHAIN_NOT_SUPPORTED;
+ if (xform != NULL) {
+ if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {
+ if (xform->next == NULL)
+ res = UADK_CHAIN_ONLY_CIPHER;
+ }
+ }
+
return res;
}
+static int
+uadk_set_session_cipher_parameters(struct rte_cryptodev *dev,
+ struct uadk_crypto_session *sess,
+ struct rte_crypto_sym_xform *xform)
+{
+ struct uadk_crypto_priv *priv = dev->data->dev_private;
+ struct rte_crypto_cipher_xform *cipher = &xform->cipher;
+ struct wd_cipher_sess_setup setup = {0};
+ struct sched_params params = {0};
+ int ret;
+
+ if (!priv->env_cipher_init) {
+ ret = wd_cipher_env_init(NULL);
+ if (ret < 0)
+ return -EINVAL;
+ priv->env_cipher_init = true;
+ }
+
+ sess->cipher.direction = cipher->op;
+ sess->iv.offset = cipher->iv.offset;
+ sess->iv.length = cipher->iv.length;
+
+ switch (cipher->algo) {
+ /* Cover supported cipher algorithms */
+ case RTE_CRYPTO_CIPHER_AES_CTR:
+ setup.alg = WD_CIPHER_AES;
+ setup.mode = WD_CIPHER_CTR;
+ sess->cipher.req.out_bytes = 64;
+ break;
+ case RTE_CRYPTO_CIPHER_AES_ECB:
+ setup.alg = WD_CIPHER_AES;
+ setup.mode = WD_CIPHER_ECB;
+ sess->cipher.req.out_bytes = 16;
+ break;
+ case RTE_CRYPTO_CIPHER_AES_CBC:
+ setup.alg = WD_CIPHER_AES;
+ setup.mode = WD_CIPHER_CBC;
+ if (cipher->key.length == 16)
+ sess->cipher.req.out_bytes = 16;
+ else
+ sess->cipher.req.out_bytes = 64;
+ break;
+ case RTE_CRYPTO_CIPHER_AES_XTS:
+ setup.alg = WD_CIPHER_AES;
+ setup.mode = WD_CIPHER_XTS;
+ if (cipher->key.length == 16)
+ sess->cipher.req.out_bytes = 32;
+ else
+ sess->cipher.req.out_bytes = 512;
+ break;
+ default:
+ ret = -ENOTSUP;
+ goto env_uninit;
+ }
+
+ params.numa_id = -1; /* choose nearby numa node */
+ setup.sched_param = ¶ms;
+ sess->handle_cipher = wd_cipher_alloc_sess(&setup);
+ if (!sess->handle_cipher) {
+ UADK_LOG(ERR, "uadk failed to alloc session!\n");
+ ret = -EINVAL;
+ goto env_uninit;
+ }
+
+ ret = wd_cipher_set_key(sess->handle_cipher, cipher->key.data, cipher->key.length);
+ if (ret) {
+ wd_cipher_free_sess(sess->handle_cipher);
+ UADK_LOG(ERR, "uadk failed to set key!\n");
+ ret = -EINVAL;
+ goto env_uninit;
+ }
+
+ return 0;
+
+env_uninit:
+ wd_cipher_env_uninit();
+ priv->env_cipher_init = false;
+ return ret;
+}
+
static int
uadk_crypto_sym_session_configure(struct rte_cryptodev *dev,
struct rte_crypto_sym_xform *xform,
struct rte_cryptodev_sym_session *session,
struct rte_mempool *mp)
{
+ struct rte_crypto_sym_xform *cipher_xform = NULL;
struct uadk_crypto_session *sess;
int ret;
@@ -263,11 +454,23 @@ uadk_crypto_sym_session_configure(struct rte_cryptodev *dev,
sess->chain_order = uadk_get_chain_order(xform);
switch (sess->chain_order) {
+ case UADK_CHAIN_ONLY_CIPHER:
+ cipher_xform = xform;
+ break;
default:
ret = -ENOTSUP;
goto err;
}
+ if (cipher_xform) {
+ ret = uadk_set_session_cipher_parameters(dev, sess, cipher_xform);
+ if (ret != 0) {
+ UADK_LOG(ERR,
+ "Invalid/unsupported cipher parameters");
+ goto err;
+ }
+ }
+
set_sym_session_private_data(session, dev->driver_id, sess);
return 0;
@@ -288,6 +491,11 @@ uadk_crypto_sym_session_clear(struct rte_cryptodev *dev,
return;
}
+ if (priv_sess->handle_cipher) {
+ wd_cipher_free_sess(priv_sess->handle_cipher);
+ priv_sess->handle_cipher = 0;
+ }
+
set_sym_session_private_data(sess, dev->driver_id, NULL);
rte_mempool_put(rte_mempool_from_obj(priv_sess), priv_sess);
}
@@ -307,12 +515,49 @@ static struct rte_cryptodev_ops uadk_crypto_pmd_ops = {
.sym_session_clear = uadk_crypto_sym_session_clear,
};
+static void
+uadk_process_cipher_op(struct rte_crypto_op *op,
+ struct uadk_crypto_session *sess,
+ struct rte_mbuf *msrc, struct rte_mbuf *mdst)
+{
+ uint32_t off = op->sym->cipher.data.offset;
+ int ret;
+
+ if (!sess) {
+ op->status = RTE_COMP_OP_STATUS_INVALID_ARGS;
+ return;
+ }
+
+ sess->cipher.req.src = rte_pktmbuf_mtod_offset(msrc, uint8_t *, off);
+ sess->cipher.req.in_bytes = op->sym->cipher.data.length;
+ sess->cipher.req.dst = rte_pktmbuf_mtod_offset(mdst, uint8_t *, off);
+ sess->cipher.req.out_buf_bytes = sess->cipher.req.in_bytes;
+ sess->cipher.req.iv_bytes = sess->iv.length;
+ sess->cipher.req.iv = rte_crypto_op_ctod_offset(op, uint8_t *,
+ sess->iv.offset);
+ if (sess->cipher.direction == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
+ sess->cipher.req.op_type = WD_CIPHER_ENCRYPTION;
+ else
+ sess->cipher.req.op_type = WD_CIPHER_DECRYPTION;
+
+ do {
+ ret = wd_do_cipher_sync(sess->handle_cipher, &sess->cipher.req);
+ } while (ret == -WD_EBUSY);
+
+ if (sess->cipher.req.out_buf_bytes > sess->cipher.req.in_bytes)
+ op->status = RTE_COMP_OP_STATUS_OUT_OF_SPACE_TERMINATED;
+
+ if (ret)
+ op->status = RTE_COMP_OP_STATUS_ERROR;
+}
+
static uint16_t
uadk_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
uint16_t nb_ops)
{
struct uadk_qp *qp = queue_pair;
struct uadk_crypto_session *sess = NULL;
+ struct rte_mbuf *msrc, *mdst;
struct rte_crypto_op *op;
uint16_t enqd = 0;
int i, ret;
@@ -320,6 +565,8 @@ uadk_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
for (i = 0; i < nb_ops; i++) {
op = ops[i];
op->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;
+ msrc = op->sym->m_src;
+ mdst = op->sym->m_dst ? op->sym->m_dst : op->sym->m_src;
if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
if (likely(op->sym->session != NULL))
@@ -330,6 +577,9 @@ uadk_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
}
switch (sess->chain_order) {
+ case UADK_CHAIN_ONLY_CIPHER:
+ uadk_process_cipher_op(op, sess, msrc, mdst);
+ break;
default:
op->status = RTE_CRYPTO_OP_STATUS_ERROR;
break;
--
2.36.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 4/5] crypto/uadk: support auth algorithms
2022-09-11 5:23 [PATCH 0/5] crypto/uadk: introduce uadk crypto driver Zhangfei Gao
` (2 preceding siblings ...)
2022-09-11 5:23 ` [PATCH 3/5] crypto/uadk: support cipher algorithms Zhangfei Gao
@ 2022-09-11 5:23 ` Zhangfei Gao
2022-09-11 5:23 ` [PATCH 5/5] doc: Update doc for UADK crypto PMD Zhangfei Gao
2022-09-13 7:08 ` [Acc] [PATCH 0/5] crypto/uadk: introduce uadk crypto driver liulongfang
5 siblings, 0 replies; 8+ messages in thread
From: Zhangfei Gao @ 2022-09-11 5:23 UTC (permalink / raw)
To: Akhil Goyal, Declan Doherty, Fan Zhang, Ashish Gupta, Ray Kinsella
Cc: dev, acc, Zhangfei Gao
Hash algorithms:
* ``RTE_CRYPTO_AUTH_MD5``
* ``RTE_CRYPTO_AUTH_MD5_HMAC``
* ``RTE_CRYPTO_AUTH_SHA1``
* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
* ``RTE_CRYPTO_AUTH_SHA224``
* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
* ``RTE_CRYPTO_AUTH_SHA256``
* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
* ``RTE_CRYPTO_AUTH_SHA384``
* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
* ``RTE_CRYPTO_AUTH_SHA512``
* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
drivers/crypto/uadk/uadk_crypto_pmd.c | 461 ++++++++++++++++++++++++++
1 file changed, 461 insertions(+)
diff --git a/drivers/crypto/uadk/uadk_crypto_pmd.c b/drivers/crypto/uadk/uadk_crypto_pmd.c
index 7ca3e3ecd8..a1196560b8 100644
--- a/drivers/crypto/uadk/uadk_crypto_pmd.c
+++ b/drivers/crypto/uadk/uadk_crypto_pmd.c
@@ -31,11 +31,15 @@ struct uadk_qp {
enum uadk_chain_order {
UADK_CHAIN_ONLY_CIPHER,
+ UADK_CHAIN_ONLY_AUTH,
+ UADK_CHAIN_CIPHER_AUTH,
+ UADK_CHAIN_AUTH_CIPHER,
UADK_CHAIN_NOT_SUPPORTED
};
struct uadk_crypto_session {
handle_t handle_cipher;
+ handle_t handle_digest;
enum uadk_chain_order chain_order;
/* IV parameters */
@@ -50,6 +54,15 @@ struct uadk_crypto_session {
/* cipher operation direction */
struct wd_cipher_req req;
} cipher;
+
+ /* Authentication Parameters */
+ struct {
+ struct wd_digest_req req;
+ enum rte_crypto_auth_operation operation;
+ /* auth operation generate or verify */
+ uint16_t digest_length;
+ /* digest length */
+ } auth;
} __rte_cache_aligned;
enum uadk_supported_platform {
@@ -59,6 +72,7 @@ enum uadk_supported_platform {
struct uadk_crypto_priv {
bool env_cipher_init;
+ bool env_auth_init;
enum uadk_supported_platform platform;
} __rte_cache_aligned;
@@ -72,6 +86,252 @@ RTE_LOG_REGISTER_DEFAULT(uadk_crypto_logtype, INFO);
## __VA_ARGS__)
static const struct rte_cryptodev_capabilities uadk_crypto_920_capabilities[] = {
+ { /* MD5 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .iv_size = { 0 }
+ }, }
+ }, }
+ },
+ { /* MD5 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_MD5,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA1 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 20,
+ .max = 20,
+ .increment = 0
+ },
+ .iv_size = { 0 }
+ }, }
+ }, }
+ },
+ { /* SHA1 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA1,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 20,
+ .max = 20,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA224 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 28,
+ .max = 28,
+ .increment = 0
+ },
+ .iv_size = { 0 }
+ }, }
+ }, }
+ },
+ { /* SHA224 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA224,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 28,
+ .max = 28,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA256 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 32,
+ .max = 32,
+ .increment = 0
+ },
+ .iv_size = { 0 }
+ }, }
+ }, }
+ },
+ { /* SHA256 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA256,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 32,
+ .max = 32,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA384 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
+ .block_size = 128,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 48,
+ .max = 48,
+ .increment = 0
+ },
+ .iv_size = { 0 }
+ }, }
+ }, }
+ },
+ { /* SHA384 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA384,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 48,
+ .max = 48,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA512 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
+ .block_size = 128,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ .iv_size = { 0 }
+ }, }
+ }, }
+ },
+ { /* SHA512 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA512,
+ .block_size = 128,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
{ /* AES ECB */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
@@ -188,6 +448,11 @@ uadk_crypto_pmd_close(struct rte_cryptodev *dev)
priv->env_cipher_init = false;
}
+ if (priv->env_auth_init) {
+ wd_digest_env_uninit();
+ priv->env_auth_init = false;
+ }
+
return 0;
}
@@ -346,9 +611,19 @@ uadk_get_chain_order(const struct rte_crypto_sym_xform *xform)
enum uadk_chain_order res = UADK_CHAIN_NOT_SUPPORTED;
if (xform != NULL) {
+ if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
+ if (xform->next == NULL)
+ res = UADK_CHAIN_ONLY_AUTH;
+ else if (xform->next->type ==
+ RTE_CRYPTO_SYM_XFORM_CIPHER)
+ res = UADK_CHAIN_AUTH_CIPHER;
+ }
+
if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {
if (xform->next == NULL)
res = UADK_CHAIN_ONLY_CIPHER;
+ else if (xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
+ res = UADK_CHAIN_CIPHER_AUTH;
}
}
@@ -435,6 +710,112 @@ uadk_set_session_cipher_parameters(struct rte_cryptodev *dev,
return ret;
}
+/* Set session auth parameters */
+static int
+uadk_set_session_auth_parameters(struct rte_cryptodev *dev,
+ struct uadk_crypto_session *sess,
+ struct rte_crypto_sym_xform *xform)
+{
+ struct uadk_crypto_priv *priv = dev->data->dev_private;
+ struct wd_digest_sess_setup setup = {0};
+ struct sched_params params = {0};
+ int ret;
+
+ if (!priv->env_auth_init) {
+ ret = wd_digest_env_init(NULL);
+ if (ret < 0)
+ return -EINVAL;
+ priv->env_auth_init = true;
+ }
+
+ sess->auth.operation = xform->auth.op;
+ sess->auth.digest_length = xform->auth.digest_length;
+
+ switch (xform->auth.algo) {
+ case RTE_CRYPTO_AUTH_MD5:
+ case RTE_CRYPTO_AUTH_MD5_HMAC:
+ setup.mode = (xform->auth.algo == RTE_CRYPTO_AUTH_MD5) ?
+ WD_DIGEST_NORMAL : WD_DIGEST_HMAC;
+ setup.alg = WD_DIGEST_MD5;
+ sess->auth.req.out_buf_bytes = 16;
+ sess->auth.req.out_bytes = 16;
+ break;
+ case RTE_CRYPTO_AUTH_SHA1:
+ case RTE_CRYPTO_AUTH_SHA1_HMAC:
+ setup.mode = (xform->auth.algo == RTE_CRYPTO_AUTH_SHA1) ?
+ WD_DIGEST_NORMAL : WD_DIGEST_HMAC;
+ setup.alg = WD_DIGEST_SHA1;
+ sess->auth.req.out_buf_bytes = 20;
+ sess->auth.req.out_bytes = 20;
+ break;
+ case RTE_CRYPTO_AUTH_SHA224:
+ case RTE_CRYPTO_AUTH_SHA224_HMAC:
+ setup.mode = (xform->auth.algo == RTE_CRYPTO_AUTH_SHA224) ?
+ WD_DIGEST_NORMAL : WD_DIGEST_HMAC;
+ setup.alg = WD_DIGEST_SHA224;
+ sess->auth.req.out_buf_bytes = 28;
+ sess->auth.req.out_bytes = 28;
+ break;
+ case RTE_CRYPTO_AUTH_SHA256:
+ case RTE_CRYPTO_AUTH_SHA256_HMAC:
+ setup.mode = (xform->auth.algo == RTE_CRYPTO_AUTH_SHA256) ?
+ WD_DIGEST_NORMAL : WD_DIGEST_HMAC;
+ setup.alg = WD_DIGEST_SHA256;
+ sess->auth.req.out_buf_bytes = 32;
+ sess->auth.req.out_bytes = 32;
+ break;
+ case RTE_CRYPTO_AUTH_SHA384:
+ case RTE_CRYPTO_AUTH_SHA384_HMAC:
+ setup.mode = (xform->auth.algo == RTE_CRYPTO_AUTH_SHA384) ?
+ WD_DIGEST_NORMAL : WD_DIGEST_HMAC;
+ setup.alg = WD_DIGEST_SHA384;
+ sess->auth.req.out_buf_bytes = 48;
+ sess->auth.req.out_bytes = 48;
+ break;
+ case RTE_CRYPTO_AUTH_SHA512:
+ case RTE_CRYPTO_AUTH_SHA512_HMAC:
+ setup.mode = (xform->auth.algo == RTE_CRYPTO_AUTH_SHA512) ?
+ WD_DIGEST_NORMAL : WD_DIGEST_HMAC;
+ setup.alg = WD_DIGEST_SHA512;
+ sess->auth.req.out_buf_bytes = 64;
+ sess->auth.req.out_bytes = 64;
+ break;
+ default:
+ ret = -ENOTSUP;
+ goto env_uninit;
+ }
+
+ params.numa_id = -1; /* choose nearby numa node */
+ setup.sched_param = ¶ms;
+ sess->handle_digest = wd_digest_alloc_sess(&setup);
+ if (!sess->handle_digest) {
+ UADK_LOG(ERR, "uadk failed to alloc session!\n");
+ ret = -EINVAL;
+ goto env_uninit;
+ }
+
+ /* if mode is HMAC, should set key */
+ if (setup.mode == WD_DIGEST_HMAC) {
+ ret = wd_digest_set_key(sess->handle_digest,
+ xform->auth.key.data,
+ xform->auth.key.length);
+ if (ret) {
+ UADK_LOG(ERR, "uadk failed to alloc session!\n");
+ wd_digest_free_sess(sess->handle_digest);
+ sess->handle_digest = 0;
+ ret = -EINVAL;
+ goto env_uninit;
+ }
+ }
+
+ return 0;
+
+env_uninit:
+ wd_digest_env_uninit();
+ priv->env_auth_init = false;
+ return ret;
+}
+
static int
uadk_crypto_sym_session_configure(struct rte_cryptodev *dev,
struct rte_crypto_sym_xform *xform,
@@ -442,6 +823,7 @@ uadk_crypto_sym_session_configure(struct rte_cryptodev *dev,
struct rte_mempool *mp)
{
struct rte_crypto_sym_xform *cipher_xform = NULL;
+ struct rte_crypto_sym_xform *auth_xform = NULL;
struct uadk_crypto_session *sess;
int ret;
@@ -457,6 +839,17 @@ uadk_crypto_sym_session_configure(struct rte_cryptodev *dev,
case UADK_CHAIN_ONLY_CIPHER:
cipher_xform = xform;
break;
+ case UADK_CHAIN_ONLY_AUTH:
+ auth_xform = xform;
+ break;
+ case UADK_CHAIN_CIPHER_AUTH:
+ cipher_xform = xform;
+ auth_xform = xform->next;
+ break;
+ case UADK_CHAIN_AUTH_CIPHER:
+ auth_xform = xform;
+ cipher_xform = xform->next;
+ break;
default:
ret = -ENOTSUP;
goto err;
@@ -471,6 +864,15 @@ uadk_crypto_sym_session_configure(struct rte_cryptodev *dev,
}
}
+ if (auth_xform) {
+ ret = uadk_set_session_auth_parameters(dev, sess, auth_xform);
+ if (ret != 0) {
+ UADK_LOG(ERR,
+ "Invalid/unsupported auth parameters");
+ goto err;
+ }
+ }
+
set_sym_session_private_data(session, dev->driver_id, sess);
return 0;
@@ -496,6 +898,11 @@ uadk_crypto_sym_session_clear(struct rte_cryptodev *dev,
priv_sess->handle_cipher = 0;
}
+ if (priv_sess->handle_digest) {
+ wd_digest_free_sess(priv_sess->handle_digest);
+ priv_sess->handle_digest = 0;
+ }
+
set_sym_session_private_data(sess, dev->driver_id, NULL);
rte_mempool_put(rte_mempool_from_obj(priv_sess), priv_sess);
}
@@ -551,6 +958,49 @@ uadk_process_cipher_op(struct rte_crypto_op *op,
op->status = RTE_COMP_OP_STATUS_ERROR;
}
+static void
+uadk_process_auth_op(struct uadk_qp *qp, struct rte_crypto_op *op,
+ struct uadk_crypto_session *sess,
+ struct rte_mbuf *msrc, struct rte_mbuf *mdst)
+{
+ uint32_t srclen = op->sym->auth.data.length;
+ uint32_t off = op->sym->auth.data.offset;
+ uint8_t *dst = qp->temp_digest;
+ int ret;
+
+ if (!sess) {
+ op->status = RTE_COMP_OP_STATUS_INVALID_ARGS;
+ return;
+ }
+
+ sess->auth.req.in = rte_pktmbuf_mtod_offset(msrc, uint8_t *, off);
+ sess->auth.req.in_bytes = srclen;
+ sess->auth.req.out = dst;
+
+ do {
+ ret = wd_do_digest_sync(sess->handle_digest, &sess->auth.req);
+ } while (ret == -WD_EBUSY);
+
+ if (sess->auth.operation == RTE_CRYPTO_AUTH_OP_VERIFY) {
+ if (memcmp(dst, op->sym->auth.digest.data,
+ sess->auth.digest_length) != 0) {
+ op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+ }
+ } else {
+ uint8_t *auth_dst;
+
+ auth_dst = op->sym->auth.digest.data;
+ if (auth_dst == NULL)
+ auth_dst = rte_pktmbuf_mtod_offset(mdst, uint8_t *,
+ op->sym->auth.data.offset +
+ op->sym->auth.data.length);
+ memcpy(auth_dst, dst, sess->auth.digest_length);
+ }
+
+ if (ret)
+ op->status = RTE_COMP_OP_STATUS_ERROR;
+}
+
static uint16_t
uadk_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
uint16_t nb_ops)
@@ -580,6 +1030,17 @@ uadk_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
case UADK_CHAIN_ONLY_CIPHER:
uadk_process_cipher_op(op, sess, msrc, mdst);
break;
+ case UADK_CHAIN_ONLY_AUTH:
+ uadk_process_auth_op(qp, op, sess, msrc, mdst);
+ break;
+ case UADK_CHAIN_CIPHER_AUTH:
+ uadk_process_cipher_op(op, sess, msrc, mdst);
+ uadk_process_auth_op(qp, op, sess, mdst, mdst);
+ break;
+ case UADK_CHAIN_AUTH_CIPHER:
+ uadk_process_auth_op(qp, op, sess, msrc, mdst);
+ uadk_process_cipher_op(op, sess, msrc, mdst);
+ break;
default:
op->status = RTE_CRYPTO_OP_STATUS_ERROR;
break;
--
2.36.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 5/5] doc: Update doc for UADK crypto PMD
2022-09-11 5:23 [PATCH 0/5] crypto/uadk: introduce uadk crypto driver Zhangfei Gao
` (3 preceding siblings ...)
2022-09-11 5:23 ` [PATCH 4/5] crypto/uadk: support auth algorithms Zhangfei Gao
@ 2022-09-11 5:23 ` Zhangfei Gao
2022-09-13 7:08 ` [Acc] [PATCH 0/5] crypto/uadk: introduce uadk crypto driver liulongfang
5 siblings, 0 replies; 8+ messages in thread
From: Zhangfei Gao @ 2022-09-11 5:23 UTC (permalink / raw)
To: Akhil Goyal, Declan Doherty, Fan Zhang, Ashish Gupta, Ray Kinsella
Cc: dev, acc, Zhangfei Gao
Update doc for the new UADK crypto PMD, which relies on UADK library [1].
UADK is a framework for user applications to access hardware accelerators.
UADK relies on IOMMU SVA (Shared Virtual Address) feature, which share
the same page table between IOMMU and MMU.
[1] https://github.com/Linaro/uadk
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
MAINTAINERS | 6 ++
doc/guides/cryptodevs/features/uadk.ini | 54 +++++++++++++++++
doc/guides/cryptodevs/index.rst | 1 +
doc/guides/cryptodevs/uadk.rst | 80 +++++++++++++++++++++++++
4 files changed, 141 insertions(+)
create mode 100644 doc/guides/cryptodevs/features/uadk.ini
create mode 100644 doc/guides/cryptodevs/uadk.rst
diff --git a/MAINTAINERS b/MAINTAINERS
index 32ffdd1a61..f485cec2ed 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1061,6 +1061,12 @@ M: Fan Zhang <roy.fan.zhang@intel.com>
F: drivers/crypto/scheduler/
F: doc/guides/cryptodevs/scheduler.rst
+HiSilicon UADK crypto
+M: Zhangfei Gao <zhangfei.gao@linaro.org>
+F: drivers/crypto/uadk/
+F: doc/guides/cryptodevs/uadk.rst
+F: doc/guides/cryptodevs/features/uadk.ini
+
Intel QuickAssist
M: Fan Zhang <roy.fan.zhang@intel.com>
F: drivers/crypto/qat/
diff --git a/doc/guides/cryptodevs/features/uadk.ini b/doc/guides/cryptodevs/features/uadk.ini
new file mode 100644
index 0000000000..1418959bd4
--- /dev/null
+++ b/doc/guides/cryptodevs/features/uadk.ini
@@ -0,0 +1,54 @@
+;
+; Supported features of the 'uadk' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+HW Accelerated = Y
+
+;
+; Supported crypto algorithms of the 'uadk' crypto driver.
+;
+[Cipher]
+AES CBC (128) = Y
+AES CBC (192) = Y
+AES CBC (256) = Y
+AES ECB (128) = Y
+AES ECB (192) = Y
+AES ECB (256) = Y
+AES XTS (128) = Y
+AES XTS (256) = Y
+DES CBC = Y
+;
+; Supported authentication algorithms of the 'uadk' crypto driver.
+;
+[Auth]
+MD5 = Y
+MD5 HMAC = Y
+SHA1 = Y
+SHA1 HMAC = Y
+SHA224 = Y
+SHA224 HMAC = Y
+SHA256 = Y
+SHA256 HMAC = Y
+SHA384 = Y
+SHA384 HMAC = Y
+SHA512 = Y
+SHA512 HMAC = Y
+
+;
+; Supported AEAD algorithms of the 'uadk' crypto driver.
+;
+[AEAD]
+
+;
+; Supported Asymmetric algorithms of the 'uadk' crypto driver.
+;
+[Asymmetric]
+
+;
+; Supported Operating systems of the 'uadk' crypto driver.
+;
+[OS]
+Linux = Y
diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst
index 39cca6dbde..cb4ce227e9 100644
--- a/doc/guides/cryptodevs/index.rst
+++ b/doc/guides/cryptodevs/index.rst
@@ -30,5 +30,6 @@ Crypto Device Drivers
scheduler
snow3g
qat
+ uadk
virtio
zuc
diff --git a/doc/guides/cryptodevs/uadk.rst b/doc/guides/cryptodevs/uadk.rst
new file mode 100644
index 0000000000..ec00b509b2
--- /dev/null
+++ b/doc/guides/cryptodevs/uadk.rst
@@ -0,0 +1,80 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright 2022-2023 Huawei Technologies Co.,Ltd. All rights reserved.
+ Copyright 2022-2023 Linaro ltd.
+
+UADK Crypto Poll Mode Driver
+=======================================================
+
+UADK crypto PMD provides poll mode driver
+All cryptographic operations are using UADK crypto API.
+Support for the following hardware accelerator devices:
+
+* ``HiSilicon Kunpeng920``
+* ``HiSilicon Kunpeng930``
+
+
+Features
+--------
+
+UADK crypto PMD has support for:
+
+Cipher algorithms:
+
+* ``RTE_CRYPTO_CIPHER_AES_ECB``
+* ``RTE_CRYPTO_CIPHER_AES_CBC``
+* ``RTE_CRYPTO_CIPHER_AES_XTS``
+* ``RTE_CRYPTO_CIPHER_DES_CBC``
+
+Hash algorithms:
+
+* ``RTE_CRYPTO_AUTH_MD5``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA1``
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA256``
+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA512``
+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
+
+Test steps
+-----------
+
+ .. code-block:: console
+
+ 1. Build
+ cd dpdk
+ mkdir build
+ meson build (--reconfigure)
+ cd build
+ ninja
+ sudo ninja install
+
+ 2. Prepare
+ echo 1024 > /sys/devices/system/node/node0/hugepages/hugepages-2048kB/nr_hugepages
+ echo 1024 > /sys/devices/system/node/node1/hugepages/hugepages-2048kB/nr_hugepages
+ echo 1024 > /sys/devices/system/node/node2/hugepages/hugepages-2048kB/nr_hugepages
+ echo 1024 > /sys/devices/system/node/node3/hugepages/hugepages-2048kB/nr_hugepages
+ mkdir -p /mnt/huge_2mb
+ mount -t hugetlbfs none /mnt/huge_2mb -o pagesize=2MB
+
+ 2 Test with crypto_uadk
+ sudo dpdk-test --vdev=crypto_uadk (--log-level=6)
+ RTE>>cryptodev_uadk_autotest
+ RTE>>quit
+
+Dependency
+------------
+
+UADK crypto PMD relies on UADK library [1]
+
+UADK is a framework for user applications to access hardware accelerators.
+UADK relies on IOMMU SVA (Shared Virtual Address) feature, which share
+the same page table between IOMMU and MMU.
+As a result, user application can directly use virtual address for device dma,
+which enhances the performance as well as easy usability.
+
+[1] https://github.com/Linaro/uadk
--
2.36.1
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [Acc] [PATCH 0/5] crypto/uadk: introduce uadk crypto driver
2022-09-11 5:23 [PATCH 0/5] crypto/uadk: introduce uadk crypto driver Zhangfei Gao
` (4 preceding siblings ...)
2022-09-11 5:23 ` [PATCH 5/5] doc: Update doc for UADK crypto PMD Zhangfei Gao
@ 2022-09-13 7:08 ` liulongfang
2022-09-15 3:02 ` Zhangfei Gao
5 siblings, 1 reply; 8+ messages in thread
From: liulongfang @ 2022-09-13 7:08 UTC (permalink / raw)
To: Zhangfei Gao, Akhil Goyal, Declan Doherty, Fan Zhang,
Ashish Gupta, Ray Kinsella
Cc: dev, acc
On 2022/9/11 13:23, Zhangfei Gao wrote:
> Introduce a new crypto PMD for UADK, which relies on UADK library [1].
>
This should be "a new crypto PMD for DPDK"
> UADK is a framework for user applications to access hardware accelerators.
> UADK relies on IOMMU SVA (Shared Virtual Address) feature, which share
> the same page table between IOMMU and MMU.
> Thereby user application can directly use virtual address for device dma,
> which enhances the performance as well as easy usability.
>
> Currently supported platforms:
> HiSilicon kunpeng920 & kunpeng930.
>
> This patch adds a basic framework.
>
> [1] https://github.com/Linaro/uadk
>
> Test:
> sudo dpdk-test --vdev=crypto_uadk (--log-level=6)
> RTE>>cryptodev_uadk_autotest
> RTE>>quit
>
> Update with rfc
>
> Suggested from Akhil Goyal <gakhil@marvell.com>
> Only consider crypto PMD first
> Split patch into small (individually compiled) patches.
> Update MAINTAINERS and doc/guides/cryptodevs/features/uadk.ini
>
> Zhangfei Gao (5):
> test/crypto: add cryptodev_uadk_autotest
> crypto/uadk: introduce uadk crypto driver
> crypto/uadk: support cipher algorithms
> crypto/uadk: support auth algorithms
> doc: Update doc for UADK crypto PMD
>
> MAINTAINERS | 6 +
> app/test/test_cryptodev.c | 7 +
> app/test/test_cryptodev.h | 1 +
> doc/guides/cryptodevs/features/uadk.ini | 54 ++
> doc/guides/cryptodevs/index.rst | 1 +
> doc/guides/cryptodevs/uadk.rst | 80 ++
> drivers/crypto/meson.build | 1 +
> drivers/crypto/uadk/meson.build | 36 +
> drivers/crypto/uadk/uadk_crypto_pmd.c | 1161 +++++++++++++++++++++++
> drivers/crypto/uadk/version.map | 3 +
> 10 files changed, 1350 insertions(+)
> create mode 100644 doc/guides/cryptodevs/features/uadk.ini
> create mode 100644 doc/guides/cryptodevs/uadk.rst
> create mode 100644 drivers/crypto/uadk/meson.build
> create mode 100644 drivers/crypto/uadk/uadk_crypto_pmd.c
> create mode 100644 drivers/crypto/uadk/version.map
>
Thanks,
Longfang
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [Acc] [PATCH 0/5] crypto/uadk: introduce uadk crypto driver
2022-09-13 7:08 ` [Acc] [PATCH 0/5] crypto/uadk: introduce uadk crypto driver liulongfang
@ 2022-09-15 3:02 ` Zhangfei Gao
0 siblings, 0 replies; 8+ messages in thread
From: Zhangfei Gao @ 2022-09-15 3:02 UTC (permalink / raw)
To: liulongfang, Zhangfei Gao, Akhil Goyal, Declan Doherty,
Fan Zhang, Ashish Gupta, Ray Kinsella
Cc: dev, acc
On 2022/9/13 下午3:08, liulongfang wrote:
> On 2022/9/11 13:23, Zhangfei Gao wrote:
>> Introduce a new crypto PMD for UADK, which relies on UADK library [1].
>>
> This should be "a new crypto PMD for DPDK"
Sorry for the misunderstanding.
Will change to this
Introduce a new crypto PMD for hardware accelerators based on UADK [1].
UADK is a framework for user applications to access hardware accelerators.
UADK relies on IOMMU SVA (Shared Virtual Address) feature, which share
the same page table between IOMMU and MMU.
Thereby user application can directly use virtual address for device dma,
which enhances the performance as well as easy usability.
[1] https://github.com/Linaro/uadk
Thanks
^ permalink raw reply [flat|nested] 8+ messages in thread