From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D21CFA0032; Mon, 12 Sep 2022 15:17:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D2BAF4282D; Mon, 12 Sep 2022 15:16:47 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2E76342B85 for ; Mon, 12 Sep 2022 15:16:46 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28CCtmqb007634 for ; Mon, 12 Sep 2022 06:16:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=rFy+Ik9fxk0ego97z8MdQR6hPvV5zl63o64x2DYlTq0=; b=hvW+YzSmH/9ujsn7UWL0dgjVJDxjwIUJ/MrQ9yHdNnY/yw4lJDLQQ+Dukf2opjoC6uPq 15Zcu2ih27H7+ybh3QaTSn7463UWXcIyhua6posgBIg1wN+MgHI2seyBDFMT4zLiv0O+ 2x0Z/pY0hJbUrTnouSNO7ZrOybEPItwS5wCtzvg3ammzw6GP/7sdhhQivsJuboq3uhbg 3zX2OOshS0HO9xTMofnQbwFQFxeLM4sDQxLMS4vGefieMcvpbXr9vuc1uxcPPedwRszj iDlyjQwX2tcZJFXeSEsTP4Bdm5VGoA6UMGJdjDGcHh0CVvQTMfArkRYt7O1iF2SWZSnT Vw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3jgt3mxt6k-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 12 Sep 2022 06:16:45 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Sep 2022 06:16:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 12 Sep 2022 06:16:42 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 6E56D3F709B; Mon, 12 Sep 2022 06:16:40 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Kommula Shiva Shankar Subject: [PATCH v3 24/32] common/cnxk: add CQ limit associated with SQ Date: Mon, 12 Sep 2022 18:44:17 +0530 Message-ID: <20220912131425.1973415-24-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220912131425.1973415-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> <20220912131425.1973415-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: AZhun7hbkNSpOi9849TzaOO7hiFKvn-e X-Proofpoint-GUID: AZhun7hbkNSpOi9849TzaOO7hiFKvn-e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-12_08,2022-09-12_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kommula Shiva Shankar Update CQ threshold limit associated with sq. This is used when we need completions for packets that are successfully transmitted. Signed-off-by: Kommula Shiva Shankar --- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index b17623076c..8869cf5169 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -346,6 +346,7 @@ struct roc_nix_sq { uint32_t nb_desc; uint16_t qid; uint16_t cqid; + uint16_t cq_drop_thresh; bool sso_ena; bool cq_ena; /* End of Input parameters */ diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index b197de0a77..60303329cc 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -907,6 +907,7 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, aq->sq.sso_ena = !!sq->sso_ena; aq->sq.cq_ena = !!sq->cq_ena; aq->sq.cq = sq->cqid; + aq->sq.cq_limit = sq->cq_drop_thresh; if (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8) aq->sq.sqe_stype = NIX_STYPE_STP; aq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle); @@ -1024,6 +1025,7 @@ sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, aq->sq.sso_ena = !!sq->sso_ena; aq->sq.cq_ena = !!sq->cq_ena; aq->sq.cq = sq->cqid; + aq->sq.cq_limit = sq->cq_drop_thresh; if (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8) aq->sq.sqe_stype = NIX_STYPE_STP; aq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle); -- 2.25.1