From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1AF41A0032; Mon, 12 Sep 2022 15:17:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B92E542B8E; Mon, 12 Sep 2022 15:16:49 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 60C624282E for ; Mon, 12 Sep 2022 15:16:48 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28CD3c1U014385 for ; Mon, 12 Sep 2022 06:16:47 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ZeYZN4/mgb0ezLv7f9olp2M1jaO9Igf5QvPuGFoGVN8=; b=QT6drG4FxX7cBp9REGh0nlTtC/T3/XI2PwCMqUrLVzbgHhia/R3OM2ZMqKlZ83/Y5PF+ jgVMaahlOCkaFlIVwqee+LRCvL1TKViqkSNJNUyPj4Xg0g0zrZ2LVAv3IM1SIye8RLwC 0t7KeKLQ90masO6wdbiFNdNJlS5YJJJBqZEV4KI0DSfK2vkQA32C8dKqSgTEr23ULEz7 QG0WiqPujUv2gP3sxyeAuGCLJ/nFZKtba4OceSCOlL03AaYpczZAmTLG7XHfUybThuM8 DTfb4Rimok383d6QHZdTKDmt/AD5PaxgddDClagt6XwAT5LVTu7IBIqKXgXkt7CQda6X 0A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3jgt3mxt71-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 12 Sep 2022 06:16:47 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 12 Sep 2022 06:16:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 12 Sep 2022 06:16:45 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 443FB3F709F; Mon, 12 Sep 2022 06:16:43 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Kommula Shiva Shankar Subject: [PATCH v3 25/32] common/cnxk: support Tx compl event via RQ to CQ mapping Date: Mon, 12 Sep 2022 18:44:18 +0530 Message-ID: <20220912131425.1973415-25-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220912131425.1973415-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> <20220912131425.1973415-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: oxwgeSGiHva-DozxVWA3efT_Om32E_81 X-Proofpoint-GUID: oxwgeSGiHva-DozxVWA3efT_Om32E_81 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-12_08,2022-09-12_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kommula Shiva Shankar This patch adds RoC support for Tx completion events via RQ to CQ mapping. Signed-off-by: Kommula Shiva Shankar --- drivers/common/cnxk/roc_nix.c | 5 ++++- drivers/common/cnxk/roc_nix.h | 2 ++ drivers/common/cnxk/roc_nix_queue.c | 7 ++----- drivers/net/cnxk/cnxk_ethdev.c | 3 +++ 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 151d8c3426..4bb306b60e 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -154,7 +154,10 @@ roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq, return rc; req->rq_cnt = nb_rxq; req->sq_cnt = nb_txq; - req->cq_cnt = nb_rxq; + if (roc_nix->tx_compl_ena) + req->cq_cnt = nb_rxq + nb_txq; + else + req->cq_cnt = nb_rxq; /* XQESZ can be W64 or W16 */ req->xqe_sz = NIX_XQESZ_W16; req->rss_sz = nix->reta_sz; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 8869cf5169..8cea3232d0 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -287,6 +287,7 @@ struct roc_nix_stats_queue { struct roc_nix_rq { /* Input parameters */ uint16_t qid; + uint16_t cqid; /* Not valid when SSO is enabled */ uint16_t bpf_id; uint64_t aura_handle; bool ipsech_ena; @@ -412,6 +413,7 @@ struct roc_nix { uint16_t max_sqb_count; enum roc_nix_rss_reta_sz reta_sz; bool enable_loop; + bool tx_compl_ena; bool hw_vlan_ins; uint8_t lock_rx_ctx; uint16_t sqb_slack; diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 60303329cc..405d9a8274 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -268,7 +268,7 @@ nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, aq->rq.good_utag = rq->tag_mask >> 24; aq->rq.bad_utag = rq->tag_mask >> 24; aq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0); - aq->rq.cq = rq->qid; + aq->rq.cq = rq->cqid; } if (rq->ipsech_ena) @@ -395,7 +395,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, aq->rq.good_utag = rq->tag_mask >> 24; aq->rq.bad_utag = rq->tag_mask >> 24; aq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0); - aq->rq.cq = rq->qid; + aq->rq.cq = rq->cqid; } if (rq->ipsech_ena) { @@ -644,9 +644,6 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) if (cq == NULL) return NIX_ERR_PARAM; - if (cq->qid >= nix->nb_rx_queues) - return NIX_ERR_QUEUE_INVALID_RANGE; - qsize = nix_qsize_clampup(cq->nb_desc); cq->nb_desc = nix_qsize_to_val(qsize); cq->qmask = cq->nb_desc - 1; diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 0603d73a90..4ed81c3d98 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -606,6 +606,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, /* Setup ROC RQ */ rq = &dev->rqs[qid]; rq->qid = qid; + rq->cqid = cq->qid; rq->aura_handle = mp->pool_id; rq->flow_tag_width = 32; rq->sso_ena = false; @@ -1168,6 +1169,8 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) if (roc_nix_is_lbk(nix)) nix->enable_loop = eth_dev->data->dev_conf.lpbk_mode; + nix->tx_compl_ena = 0; + /* Alloc a nix lf */ rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg); if (rc) { -- 2.25.1