From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A1D91A0032; Mon, 12 Sep 2022 15:17:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8D47B42B93; Mon, 12 Sep 2022 15:16:54 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 65D8B42847 for ; Mon, 12 Sep 2022 15:16:53 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28BNN4M5010075 for ; Mon, 12 Sep 2022 06:16:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Il0vrrFTQVpJ+uURr6asL+NR1sUJ8dk7/iPIc91dIn8=; b=JLxm1yjcOqI0iGcFbf4t+saTQ9gHNG/8fAxVlTS8L/vMUgqRGfbqIDJikveK9G3E31aG EU0G09MD6VtEz/C7zoIigwZel4h7lc5p39Uo1uWO2vweO1391i87fiyMJE9ZYb03Qsbs lGn0R0k5CeI+VN+5yG3rnzpolFJuUemEt5HNy0qxrUm7X/tl0YTfsD1tDXmMbbhBvSu8 BBZivnKjU56XOy5U1YBFBD9AL7z8MfCLdXCqlQSwUl3Mrf+hrt11UQiAVNc55eoSdDNQ 7Smiv/cwKiWT+FWop8BsDFitSG3GHiUIM0Tkyq9FsEnUMRfOCNzP7T49lwf+YFY1giZ/ EQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3jgt3mxt7n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 12 Sep 2022 06:16:52 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 12 Sep 2022 06:16:50 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 12 Sep 2022 06:16:50 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id AC0E13F709F; Mon, 12 Sep 2022 06:16:48 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v3 27/32] net/cnxk: limit port specific SA table size Date: Mon, 12 Sep 2022 18:44:20 +0530 Message-ID: <20220912131425.1973415-27-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220912131425.1973415-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> <20220912131425.1973415-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: Lhg0pESB9Pge4-JBqnDzA8kWPeXpJAkf X-Proofpoint-GUID: Lhg0pESB9Pge4-JBqnDzA8kWPeXpJAkf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-12_08,2022-09-12_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Limit port specific SA table size to 1 entry when not used. This is useful when inline device is enabled as then Port specific SA table will not be used for Inline IPsec inbound processing. Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cnxk_ethdev.c | 4 ++++ drivers/net/cnxk/cnxk_ethdev.h | 5 ++++- drivers/net/cnxk/cnxk_ethdev_devargs.c | 3 +-- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 4ed81c3d98..89f8cc107d 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -103,6 +103,10 @@ nix_security_setup(struct cnxk_eth_dev *dev) int i, rc = 0; if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) { + /* Setup minimum SA table when inline device is used */ + nix->ipsec_in_min_spi = dev->inb.no_inl_dev ? dev->inb.min_spi : 0; + nix->ipsec_in_max_spi = dev->inb.no_inl_dev ? dev->inb.max_spi : 1; + /* Setup Inline Inbound */ rc = roc_nix_inl_inb_init(nix); if (rc) { diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index a4178cfeff..bed0e0eada 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -273,8 +273,11 @@ TAILQ_HEAD(cnxk_eth_sec_sess_list, cnxk_eth_sec_sess); /* Inbound security data */ struct cnxk_eth_dev_sec_inb { + /* IPSec inbound min SPI */ + uint32_t min_spi; + /* IPSec inbound max SPI */ - uint16_t max_spi; + uint32_t max_spi; /* Using inbound with inline device */ bool inl_dev; diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c index 4ded850622..d28509dbda 100644 --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c @@ -320,12 +320,11 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) null_devargs: dev->scalar_ena = !!scalar_enable; dev->inb.no_inl_dev = !!no_inl_dev; + dev->inb.min_spi = ipsec_in_min_spi; dev->inb.max_spi = ipsec_in_max_spi; dev->outb.max_sa = ipsec_out_max_sa; dev->outb.nb_desc = outb_nb_desc; dev->outb.nb_crypto_qs = outb_nb_crypto_qs; - dev->nix.ipsec_in_min_spi = ipsec_in_min_spi; - dev->nix.ipsec_in_max_spi = ipsec_in_max_spi; dev->nix.ipsec_out_max_sa = ipsec_out_max_sa; dev->nix.rss_tag_as_xor = !!rss_tag_as_xor; dev->nix.max_sqb_count = sqb_count; -- 2.25.1