From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 128E7A0032; Mon, 12 Sep 2022 15:15:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BB6B8427F4; Mon, 12 Sep 2022 15:15:44 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 73774427F4 for ; Mon, 12 Sep 2022 15:15:43 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28BNFFdc001505 for ; Mon, 12 Sep 2022 06:15:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=GReAE5rfYbvPMkzMOaobGtYqTSDRJutCs51rS1UgdLk=; b=k4eypQ4JLEmDCq8WyIJjLEumBKZn80EKBGMezXYxZNy4EjfL5GbrCisBgMesZvPEzhGG fmbR+fPGMAtaGOsqNFm4Xssr2aFSyIT2S0798HjefDhTkX4mk2gc/smPw/vLcHHzpfYn PBS03bNLDGA+rCQvNl71ayUunZ97bpvIF0bIsuzW7P/6dkPUz3Ks1hiCEMkIhh0iL9D5 rwCpBU0+U+Zgjt0LlMzeOuWiZDpoS0DHuStJ7UliyOy5PS9Ha6pBjQ55Mmvjn/nSBMx0 TrWQs7uUAy1NgbEm3TNmDm4xA0zYhbgonl5lUguMdjhhCuOipMOWSkExIpKWmKdDOZtJ AA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3jgqxq76u8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 12 Sep 2022 06:15:42 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 12 Sep 2022 06:15:40 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 12 Sep 2022 06:15:40 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 8CB493F709F; Mon, 12 Sep 2022 06:15:38 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Harman Kalra Subject: [PATCH v3 03/32] common/cnxk: fix part value for cn10k Date: Mon, 12 Sep 2022 18:43:56 +0530 Message-ID: <20220912131425.1973415-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220912131425.1973415-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> <20220912131425.1973415-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: Zi6xgS7s6w7Vf3oJBexBdsYLWAx1TVaf X-Proofpoint-GUID: Zi6xgS7s6w7Vf3oJBexBdsYLWAx1TVaf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-12_08,2022-09-12_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Harman Kalra Updating the logic for getting part and pass value for cn10k family, as device tree compatible logic does not work in VMs. Scanning all the PCI device and detect first RVU device, subsystem device file gives part no and revision file provide pass information. Fixes: 014a9e222bac ("common/cnxk: add model init and IO handling API") Signed-off-by: Harman Kalra --- drivers/common/cnxk/roc_model.c | 152 +++++++++++++++++++++-------- drivers/common/cnxk/roc_platform.h | 3 + 2 files changed, 113 insertions(+), 42 deletions(-) diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c index c934a10509..626de60fb0 100644 --- a/drivers/common/cnxk/roc_model.c +++ b/drivers/common/cnxk/roc_model.c @@ -2,6 +2,7 @@ * Copyright(C) 2021 Marvell. */ +#include #include #include @@ -40,6 +41,16 @@ struct roc_model *roc_model; #define MODEL_MINOR_SHIFT 0 #define MODEL_MINOR_MASK ((1 << MODEL_MINOR_BITS) - 1) +#define MODEL_CN10K_PART_SHIFT 8 +#define MODEL_CN10K_PASS_BITS 4 +#define MODEL_CN10K_PASS_MASK ((1 << MODEL_CN10K_PASS_BITS) - 1) +#define MODEL_CN10K_MAJOR_BITS 2 +#define MODEL_CN10K_MAJOR_SHIFT 2 +#define MODEL_CN10K_MAJOR_MASK ((1 << MODEL_CN10K_MAJOR_BITS) - 1) +#define MODEL_CN10K_MINOR_BITS 2 +#define MODEL_CN10K_MINOR_SHIFT 0 +#define MODEL_CN10K_MINOR_MASK ((1 << MODEL_CN10K_MINOR_BITS) - 1) + static const struct model_db { uint32_t impl; uint32_t part; @@ -66,55 +77,101 @@ static const struct model_db { {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0, "cnf95xxmm_a0"}}; -static uint32_t -cn10k_part_get(void) +/* Detect if RVU device */ +static bool +is_rvu_device(unsigned long val) { - uint32_t soc = 0x0; - char buf[BUFSIZ]; - char *ptr; - FILE *fd; - - /* Read the CPU compatible variant */ - fd = fopen("/proc/device-tree/compatible", "r"); - if (!fd) { - plt_err("Failed to open /proc/device-tree/compatible"); - goto err; - } + return (val == PCI_DEVID_CNXK_RVU_PF || val == PCI_DEVID_CNXK_RVU_VF || + val == PCI_DEVID_CNXK_RVU_AF || + val == PCI_DEVID_CNXK_RVU_AF_VF || + val == PCI_DEVID_CNXK_RVU_NPA_PF || + val == PCI_DEVID_CNXK_RVU_NPA_VF || + val == PCI_DEVID_CNXK_RVU_SSO_TIM_PF || + val == PCI_DEVID_CNXK_RVU_SSO_TIM_VF || + val == PCI_DEVID_CN10K_RVU_CPT_PF || + val == PCI_DEVID_CN10K_RVU_CPT_VF); +} - if (fgets(buf, sizeof(buf), fd) == NULL) { - plt_err("Failed to read from /proc/device-tree/compatible"); - goto fclose; - } - ptr = strchr(buf, ','); - if (!ptr) { - plt_err("Malformed 'CPU compatible': <%s>", buf); - goto fclose; - } - ptr++; - if (strcmp("cn10ka", ptr) == 0) { - soc = PART_106xx; - } else if (strcmp("cnf10ka", ptr) == 0) { - soc = PART_105xx; - } else if (strcmp("cnf10kb", ptr) == 0) { - soc = PART_105xxN; - } else if (strcmp("cn10kb", ptr) == 0) { - soc = PART_103xx; - } else { - plt_err("Unidentified 'CPU compatible': <%s>", ptr); - goto fclose; +static int +rvu_device_lookup(const char *dirname, uint32_t *part, uint32_t *pass) +{ + char filename[PATH_MAX]; + unsigned long val; + + /* Check if vendor id is cavium */ + snprintf(filename, sizeof(filename), "%s/vendor", dirname); + if (plt_sysfs_value_parse(filename, &val) < 0) + goto error; + + if (val != PCI_VENDOR_ID_CAVIUM) + goto error; + + /* Get device id */ + snprintf(filename, sizeof(filename), "%s/device", dirname); + if (plt_sysfs_value_parse(filename, &val) < 0) + goto error; + + /* Check if device ID belongs to any RVU device */ + if (!is_rvu_device(val)) + goto error; + + /* Get subsystem_device id */ + snprintf(filename, sizeof(filename), "%s/subsystem_device", dirname); + if (plt_sysfs_value_parse(filename, &val) < 0) + goto error; + + *part = val >> MODEL_CN10K_PART_SHIFT; + + /* Get revision for pass value*/ + snprintf(filename, sizeof(filename), "%s/revision", dirname); + if (plt_sysfs_value_parse(filename, &val) < 0) + goto error; + + *pass = val & MODEL_CN10K_PASS_MASK; + + return 0; +error: + return -EINVAL; +} + +/* Scans through all PCI devices, detects RVU device and returns + * subsystem_device + */ +static int +cn10k_part_pass_get(uint32_t *part, uint32_t *pass) +{ +#define SYSFS_PCI_DEVICES "/sys/bus/pci/devices" + char dirname[PATH_MAX]; + struct dirent *e; + DIR *dir; + + dir = opendir(SYSFS_PCI_DEVICES); + if (dir == NULL) { + plt_err("%s(): opendir failed: %s\n", __func__, + strerror(errno)); + return -errno; } -fclose: - fclose(fd); + while ((e = readdir(dir)) != NULL) { + if (e->d_name[0] == '.') + continue; + + snprintf(dirname, sizeof(dirname), "%s/%s", SYSFS_PCI_DEVICES, + e->d_name); + + /* Lookup for rvu device and get part pass information */ + if (!rvu_device_lookup(dirname, part, pass)) + break; + } -err: - return soc; + closedir(dir); + return 0; } static bool populate_model(struct roc_model *model, uint32_t midr) { - uint32_t impl, major, part, minor; + uint32_t impl, major, part, minor, pass; bool found = false; size_t i; @@ -124,8 +181,19 @@ populate_model(struct roc_model *model, uint32_t midr) minor = (midr >> MODEL_MINOR_SHIFT) & MODEL_MINOR_MASK; /* Update part number for cn10k from device-tree */ - if (part == SOC_PART_CN10K) - part = cn10k_part_get(); + if (part == SOC_PART_CN10K) { + if (cn10k_part_pass_get(&part, &pass)) + goto not_found; + /* + * Pass value format: + * Bits 0..1: minor pass + * Bits 3..2: major pass + */ + minor = (pass >> MODEL_CN10K_MINOR_SHIFT) & + MODEL_CN10K_MINOR_MASK; + major = (pass >> MODEL_CN10K_MAJOR_SHIFT) & + MODEL_CN10K_MAJOR_MASK; + } for (i = 0; i < PLT_DIM(model_db); i++) if (model_db[i].impl == impl && model_db[i].part == part && @@ -136,7 +204,7 @@ populate_model(struct roc_model *model, uint32_t midr) found = true; break; } - +not_found: if (!found) { model->flag = 0; strncpy(model->name, "unknown", ROC_MODEL_STR_LEN_MAX - 1); diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 502f243a81..3e7adfc5b8 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -24,6 +24,8 @@ #include #include +#include "eal_filesystem.h" + #include "roc_bits.h" #if defined(__ARM_FEATURE_SVE) @@ -94,6 +96,7 @@ #define plt_pci_device rte_pci_device #define plt_pci_read_config rte_pci_read_config #define plt_pci_find_ext_capability rte_pci_find_ext_capability +#define plt_sysfs_value_parse eal_parse_sysfs_value #define plt_log2_u32 rte_log2_u32 #define plt_cpu_to_be_16 rte_cpu_to_be_16 -- 2.25.1