From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>,
Ashwin Sekhar T K <asekhar@marvell.com>,
Pavan Nikhilesh <pbhagavatula@marvell.com>
Cc: <jerinj@marvell.com>, <dev@dpdk.org>
Subject: [PATCH v3 09/32] common/cnxk: reserve aura zero on cn10ka NPA
Date: Mon, 12 Sep 2022 18:44:02 +0530 [thread overview]
Message-ID: <20220912131425.1973415-9-ndabilpuram@marvell.com> (raw)
In-Reply-To: <20220912131425.1973415-1-ndabilpuram@marvell.com>
Reserve aura id 0 on cn10k and provide mechanism to
specifically allocate it and free it via roc_npa_*
API's.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
drivers/common/cnxk/roc_dpi.c | 2 +-
drivers/common/cnxk/roc_nix_queue.c | 2 +-
drivers/common/cnxk/roc_npa.c | 100 +++++++++++++++++++-----
drivers/common/cnxk/roc_npa.h | 6 +-
drivers/common/cnxk/roc_npa_priv.h | 1 +
drivers/common/cnxk/roc_sso.c | 2 +-
drivers/common/cnxk/version.map | 1 +
drivers/mempool/cnxk/cnxk_mempool_ops.c | 7 +-
8 files changed, 97 insertions(+), 24 deletions(-)
diff --git a/drivers/common/cnxk/roc_dpi.c b/drivers/common/cnxk/roc_dpi.c
index 23b2cc41a4..93c8318a3d 100644
--- a/drivers/common/cnxk/roc_dpi.c
+++ b/drivers/common/cnxk/roc_dpi.c
@@ -75,7 +75,7 @@ roc_dpi_configure(struct roc_dpi *roc_dpi)
memset(&aura, 0, sizeof(aura));
rc = roc_npa_pool_create(&aura_handle, DPI_CMD_QUEUE_SIZE,
- DPI_CMD_QUEUE_BUFS, &aura, &pool);
+ DPI_CMD_QUEUE_BUFS, &aura, &pool, 0);
if (rc) {
plt_err("Failed to create NPA pool, err %d\n", rc);
return rc;
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 692b13415a..70b4516eca 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -713,7 +713,7 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
aura.fc_addr = (uint64_t)sq->fc;
aura.fc_hyst_bits = 0; /* Store count on all updates */
rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura,
- &pool);
+ &pool, 0);
if (rc)
goto fail;
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index 1e60f443f0..760a2315b2 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -260,16 +260,60 @@ bitmap_ctzll(uint64_t slab)
return __builtin_ctzll(slab);
}
+static int
+find_free_aura(struct npa_lf *lf, uint32_t flags)
+{
+ struct plt_bitmap *bmp = lf->npa_bmp;
+ uint64_t aura0_state = 0;
+ uint64_t slab;
+ uint32_t pos;
+ int idx = -1;
+ int rc;
+
+ if (flags & ROC_NPA_ZERO_AURA_F) {
+ /* Only look for zero aura */
+ if (plt_bitmap_get(bmp, 0))
+ return 0;
+ plt_err("Zero aura already in use");
+ return -1;
+ }
+
+ if (lf->zero_aura_rsvd) {
+ /* Save and clear zero aura bit if needed */
+ aura0_state = plt_bitmap_get(bmp, 0);
+ if (aura0_state)
+ plt_bitmap_clear(bmp, 0);
+ }
+
+ pos = 0;
+ slab = 0;
+ /* Scan from the beginning */
+ plt_bitmap_scan_init(bmp);
+ /* Scan bitmap to get the free pool */
+ rc = plt_bitmap_scan(bmp, &pos, &slab);
+ /* Empty bitmap */
+ if (rc == 0) {
+ plt_err("Aura's exhausted");
+ goto empty;
+ }
+
+ idx = pos + bitmap_ctzll(slab);
+empty:
+ if (lf->zero_aura_rsvd && aura0_state)
+ plt_bitmap_set(bmp, 0);
+
+ return idx;
+}
+
static int
npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
const uint32_t block_count, struct npa_aura_s *aura,
- struct npa_pool_s *pool, uint64_t *aura_handle)
+ struct npa_pool_s *pool, uint64_t *aura_handle,
+ uint32_t flags)
{
int rc, aura_id, pool_id, stack_size, alloc_size;
char name[PLT_MEMZONE_NAMESIZE];
const struct plt_memzone *mz;
- uint64_t slab;
- uint32_t pos;
/* Sanity check */
if (!lf || !block_size || !block_count || !pool || !aura ||
@@ -281,20 +325,11 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
block_size > ROC_NPA_MAX_BLOCK_SZ)
return NPA_ERR_INVALID_BLOCK_SZ;
- pos = 0;
- slab = 0;
- /* Scan from the beginning */
- plt_bitmap_scan_init(lf->npa_bmp);
- /* Scan bitmap to get the free pool */
- rc = plt_bitmap_scan(lf->npa_bmp, &pos, &slab);
- /* Empty bitmap */
- if (rc == 0) {
- plt_err("Mempools exhausted");
- return NPA_ERR_AURA_ID_ALLOC;
- }
-
/* Get aura_id from resource bitmap */
- aura_id = pos + bitmap_ctzll(slab);
+ aura_id = find_free_aura(lf, flags);
+ if (aura_id < 0)
+ return NPA_ERR_AURA_ID_ALLOC;
+
/* Mark pool as reserved */
plt_bitmap_clear(lf->npa_bmp, aura_id);
@@ -374,7 +409,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
int
roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size,
uint32_t block_count, struct npa_aura_s *aura,
- struct npa_pool_s *pool)
+ struct npa_pool_s *pool, uint32_t flags)
{
struct npa_aura_s defaura;
struct npa_pool_s defpool;
@@ -394,6 +429,11 @@ roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size,
goto error;
}
+ if (flags & ROC_NPA_ZERO_AURA_F && !lf->zero_aura_rsvd) {
+ rc = NPA_ERR_ALLOC;
+ goto error;
+ }
+
if (aura == NULL) {
memset(&defaura, 0, sizeof(struct npa_aura_s));
aura = &defaura;
@@ -406,7 +446,7 @@ roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size,
}
rc = npa_aura_pool_pair_alloc(lf, block_size, block_count, aura, pool,
- aura_handle);
+ aura_handle, flags);
if (rc) {
plt_err("Failed to alloc pool or aura rc=%d", rc);
goto error;
@@ -522,6 +562,26 @@ roc_npa_pool_range_update_check(uint64_t aura_handle)
return 0;
}
+uint64_t
+roc_npa_zero_aura_handle(void)
+{
+ struct idev_cfg *idev;
+ struct npa_lf *lf;
+
+ lf = idev_npa_obj_get();
+ if (lf == NULL)
+ return NPA_ERR_DEVICE_NOT_BOUNDED;
+
+ idev = idev_get_cfg();
+ if (idev == NULL)
+ return NPA_ERR_ALLOC;
+
+ /* Return aura handle only if reserved */
+ if (lf->zero_aura_rsvd)
+ return roc_npa_aura_handle_gen(0, lf->base);
+ return 0;
+}
+
static inline int
npa_attach(struct mbox *mbox)
{
@@ -672,6 +732,10 @@ npa_dev_init(struct npa_lf *lf, uintptr_t base, struct mbox *mbox)
for (i = 0; i < nr_pools; i++)
plt_bitmap_set(lf->npa_bmp, i);
+ /* Reserve zero aura for all models other than CN9K */
+ if (!roc_model_is_cn9k())
+ lf->zero_aura_rsvd = true;
+
/* Allocate memory for qint context */
lf->npa_qint_mem = plt_zmalloc(sizeof(struct npa_qint) * nr_pools, 0);
if (lf->npa_qint_mem == NULL) {
diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 59d13d88a1..69129cb4cc 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -711,10 +711,13 @@ struct roc_npa {
int __roc_api roc_npa_dev_init(struct roc_npa *roc_npa);
int __roc_api roc_npa_dev_fini(struct roc_npa *roc_npa);
+/* Flags to pool create */
+#define ROC_NPA_ZERO_AURA_F BIT(0)
+
/* NPA pool */
int __roc_api roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size,
uint32_t block_count, struct npa_aura_s *aura,
- struct npa_pool_s *pool);
+ struct npa_pool_s *pool, uint32_t flags);
int __roc_api roc_npa_aura_limit_modify(uint64_t aura_handle,
uint16_t aura_limit);
int __roc_api roc_npa_pool_destroy(uint64_t aura_handle);
@@ -722,6 +725,7 @@ int __roc_api roc_npa_pool_range_update_check(uint64_t aura_handle);
void __roc_api roc_npa_aura_op_range_set(uint64_t aura_handle,
uint64_t start_iova,
uint64_t end_iova);
+uint64_t __roc_api roc_npa_zero_aura_handle(void);
/* Init callbacks */
typedef int (*roc_npa_lf_init_cb_t)(struct plt_pci_device *pci_dev);
diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h
index 5a02a61e00..de3d5448ba 100644
--- a/drivers/common/cnxk/roc_npa_priv.h
+++ b/drivers/common/cnxk/roc_npa_priv.h
@@ -32,6 +32,7 @@ struct npa_lf {
uint8_t aura_sz;
uint32_t qints;
uintptr_t base;
+ bool zero_aura_rsvd;
};
struct npa_qint {
diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c
index 126a9cba99..4bee5a97e1 100644
--- a/drivers/common/cnxk/roc_sso.c
+++ b/drivers/common/cnxk/roc_sso.c
@@ -473,7 +473,7 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq,
aura.fc_addr = (uint64_t)xaq->fc;
aura.fc_hyst_bits = 0; /* Store count on all updates */
rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq,
- &aura, &pool);
+ &aura, &pool, 0);
if (rc) {
plt_err("Failed to create XAQ pool");
goto npa_fail;
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 6d43e37d1e..6c05e893e3 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -318,6 +318,7 @@ INTERNAL {
roc_npa_pool_destroy;
roc_npa_pool_op_pc_reset;
roc_npa_pool_range_update_check;
+ roc_npa_zero_aura_handle;
roc_npc_fini;
roc_npc_flow_create;
roc_npc_flow_destroy;
diff --git a/drivers/mempool/cnxk/cnxk_mempool_ops.c b/drivers/mempool/cnxk/cnxk_mempool_ops.c
index c7b75f026d..a0b94bb95c 100644
--- a/drivers/mempool/cnxk/cnxk_mempool_ops.c
+++ b/drivers/mempool/cnxk/cnxk_mempool_ops.c
@@ -72,10 +72,10 @@ cnxk_mempool_calc_mem_size(const struct rte_mempool *mp, uint32_t obj_num,
int
cnxk_mempool_alloc(struct rte_mempool *mp)
{
+ uint32_t block_count, flags = 0;
uint64_t aura_handle = 0;
struct npa_aura_s aura;
struct npa_pool_s pool;
- uint32_t block_count;
size_t block_size;
int rc = -ERANGE;
@@ -100,8 +100,11 @@ cnxk_mempool_alloc(struct rte_mempool *mp)
if (mp->pool_config != NULL)
memcpy(&aura, mp->pool_config, sizeof(struct npa_aura_s));
+ if (aura.ena && aura.pool_addr == 0)
+ flags = ROC_NPA_ZERO_AURA_F;
+
rc = roc_npa_pool_create(&aura_handle, block_size, block_count, &aura,
- &pool);
+ &pool, flags);
if (rc) {
plt_err("Failed to alloc pool or aura rc=%d", rc);
goto error;
--
2.25.1
next prev parent reply other threads:[~2022-09-12 13:18 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-09 18:48 [PATCH 01/23] common/cnxk: fix part value for cn10k Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 02/23] common/cnxk: add cn10ka A1 platform Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 03/23] common/cnxk: update inbound inline IPsec config mailbox Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 04/23] net/cnxk: fix missing fc wait for outbound path in vec mode Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 05/23] common/cnxk: limit meta aura workaround to CN10K A0 Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 06/23] common/cnxk: delay inline device RQ enable to dev start Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 07/23] common/cnxk: reserve aura zero on cn10ka NPA Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 08/23] common/cnxk: add support to set NPA buf type Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 09/23] common/cnxk: update attributes to pools used by NIX Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 10/23] common/cnxk: support zero aura for inline inbound meta Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 11/23] net/cnxk: support for zero aura for inline meta Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 12/23] common/cnxk: avoid the use of platform specific APIs Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 13/23] net/cnxk: use full context IPsec structures in fp Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 14/23] net/cnxk: add crypto capabilities for HMAC-SHA2 Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 15/23] common/cnxk: enable aging on CN10K platform Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 16/23] common/cnxk: updated shaper profile with red algorithm Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 17/23] common/cnxk: add 98xx A1 platform Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 18/23] net/cnxk: enable additional ciphers for inline Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 19/23] net/cnxk: enable 3des-cbc cipher capability Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 20/23] net/cnxk: skip PFC configuration on LBK Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 21/23] common/cnxk: add support for CPT second pass Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 22/23] common/cnxk: add CQ limit associated with SQ Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 23/23] common/cnxk: support Tx compl event via RQ to CQ mapping Nithin Dabilpuram
2022-08-30 4:51 ` [PATCH 01/23] common/cnxk: fix part value for cn10k Jerin Jacob
2022-08-30 5:16 ` [EXT] " Nithin Kumar Dabilpuram
2022-09-05 13:31 ` [PATCH v2 01/31] cnxk/net: add fc check in vector event Tx path Nithin Dabilpuram
2022-09-05 13:31 ` [PATCH v2 02/31] common/cnxk: fix part value for cn10k Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 03/31] common/cnxk: add cn10ka A1 platform Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 04/31] common/cnxk: update inbound inline IPsec config mailbox Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 05/31] net/cnxk: fix missing fc wait for outbound path in vec mode Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 06/31] common/cnxk: limit meta aura workaround to CN10K A0 Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 07/31] common/cnxk: delay inline device RQ enable to dev start Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 08/31] common/cnxk: reserve aura zero on cn10ka NPA Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 09/31] common/cnxk: add support to set NPA buf type Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 10/31] common/cnxk: update attributes to pools used by NIX Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 11/31] common/cnxk: support zero aura for inline inbound meta Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 12/31] net/cnxk: support for zero aura for inline meta Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 13/31] common/cnxk: avoid the use of platform specific APIs Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 14/31] net/cnxk: use full context IPsec structures in fp Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 15/31] net/cnxk: add crypto capabilities for HMAC-SHA2 Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 16/31] common/cnxk: enable aging on CN10K platform Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 17/31] common/cnxk: updated shaper profile with red algorithm Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 18/31] common/cnxk: add 98xx A1 platform Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 19/31] net/cnxk: enable additional ciphers for inline Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 20/31] net/cnxk: enable 3des-cbc cipher capability Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 21/31] net/cnxk: skip PFC configuration on LBK Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 22/31] common/cnxk: add support for CPT second pass Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 23/31] common/cnxk: add CQ limit associated with SQ Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 24/31] common/cnxk: support Tx compl event via RQ to CQ mapping Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 25/31] event/cnxk: wait for CPT fc on wqe path Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 26/31] net/cnxk: limit port specific SA table size Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 27/31] net/cnxk: add support for crypto cipher DES-CBC Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 28/31] net/cnxk: Add support for crypto auth alg MD5 Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 29/31] net/cnxk: enable esn and antireplay support Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 30/31] common/cnxk: dump device basic info to file Nithin Dabilpuram
2022-09-05 13:32 ` [PATCH v2 31/31] net/cnxk: dumps device private information Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 01/32] net/cnxk: add eth port specific PTP enable Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 02/32] cnxk/net: add fc check in vector event Tx path Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 03/32] common/cnxk: fix part value for cn10k Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 04/32] common/cnxk: add cn10ka A1 platform Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 05/32] common/cnxk: update inbound inline IPsec config mailbox Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 06/32] net/cnxk: fix missing fc wait for outbound path in vec mode Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 07/32] common/cnxk: limit meta aura workaround to CN10K A0 Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 08/32] common/cnxk: delay inline device RQ enable to dev start Nithin Dabilpuram
2022-09-12 13:14 ` Nithin Dabilpuram [this message]
2022-09-12 13:14 ` [PATCH v3 10/32] common/cnxk: add support to set NPA buf type Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 11/32] common/cnxk: update attributes to pools used by NIX Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 12/32] common/cnxk: support zero aura for inline inbound meta Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 13/32] net/cnxk: support for zero aura for inline meta Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 14/32] common/cnxk: avoid the use of platform specific APIs Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 15/32] net/cnxk: use full context IPsec structures in fp Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 16/32] net/cnxk: add crypto capabilities for HMAC-SHA2 Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 17/32] common/cnxk: enable aging on CN10K platform Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 18/32] common/cnxk: updated shaper profile with red algorithm Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 19/32] common/cnxk: add 98xx A1 platform Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 20/32] net/cnxk: enable additional ciphers for inline Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 21/32] net/cnxk: enable 3des-cbc cipher capability Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 22/32] net/cnxk: skip PFC configuration on LBK Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 23/32] common/cnxk: add support for CPT second pass Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 24/32] common/cnxk: add CQ limit associated with SQ Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 25/32] common/cnxk: support Tx compl event via RQ to CQ mapping Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 26/32] event/cnxk: wait for CPT fc on wqe path Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 27/32] net/cnxk: limit port specific SA table size Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 28/32] net/cnxk: add support for crypto cipher DES-CBC Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 29/32] net/cnxk: add support for crypto auth alg MD5 Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 30/32] net/cnxk: enable esn and antireplay support Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 31/32] common/cnxk: dump device basic info to file Nithin Dabilpuram
2022-09-12 13:14 ` [PATCH v3 32/32] net/cnxk: dumps device private information Nithin Dabilpuram
2022-09-16 11:36 ` Jerin Jacob
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220912131425.1973415-9-ndabilpuram@marvell.com \
--to=ndabilpuram@marvell.com \
--cc=asekhar@marvell.com \
--cc=dev@dpdk.org \
--cc=jerinj@marvell.com \
--cc=kirankumark@marvell.com \
--cc=mdr@ashroe.eu \
--cc=pbhagavatula@marvell.com \
--cc=skori@marvell.com \
--cc=skoteshwar@marvell.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).