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Received-SPF: Pass (protection.outlook.com: domain of ddn.com designates 50.222.100.11 as permitted sender) receiver=protection.outlook.com; client-ip=50.222.100.11; helo=uww-mx01.datadirectnet.com; pr=C Received: from uww-mx01.datadirectnet.com (50.222.100.11) by DM6NAM04FT061.mail.protection.outlook.com (10.13.159.64) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5612.13 via Frontend Transport; Mon, 12 Sep 2022 16:02:11 +0000 Received: from localhost (unknown [10.68.0.8]) by uww-mx01.datadirectnet.com (Postfix) with ESMTP id E1A7D20C684B; Mon, 12 Sep 2022 10:03:21 -0600 (MDT) From: Michael Piszczek To: Cc: dev@dpdk.org, Michael Piszczek Subject: [PATCH 1/1] pci: read amd iommu virtual address width Date: Mon, 12 Sep 2022 18:01:57 +0200 Message-Id: <20220912160157.3642968-2-mpiszczek@ddn.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220912160157.3642968-1-mpiszczek@ddn.com> References: <20220912160157.3642968-1-mpiszczek@ddn.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM04FT061:EE_|MN0PR19MB5753:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 077e0e51-b2b9-4970-8f7d-08da94d826d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Michael Piszczek --- drivers/bus/pci/linux/pci.c | 42 +++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c index e521459870..df9da78e45 100644 --- a/drivers/bus/pci/linux/pci.c +++ b/drivers/bus/pci/linux/pci.c @@ -492,6 +492,38 @@ rte_pci_scan(void) } #if defined(RTE_ARCH_X86) + +static uint64_t +pci_device_amd_iommu_support_va(const struct rte_pci_addr *addr) +{ +#define RD_AMD_CAP_VASIZE_SHIFT 15 +#define RD_AMD_CAP_VASIZE_MASK (0x7F << RD_AMD_CAP_VASIZE_SHIFT) + + char filename[PATH_MAX]; + FILE *fp; + uint64_t amd_cap_reg = 0; + + snprintf(filename, sizeof(filename), + "%s/" PCI_PRI_FMT "/iommu/amd-iommu/cap", + rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid, + addr->function); + + fp = fopen(filename, "r"); + if (fp == NULL) + return 0; + + /* We have an Amd IOMMU */ + if (fscanf(fp, "%" PRIx64, &amd_cap_reg) != 1) { + RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename); + fclose(fp); + return 0; + } + + fclose(fp); + + return ((amd_cap_reg & RD_AMD_CAP_VASIZE_MASK) >> RD_AMD_CAP_VASIZE_SHIFT) + 1; +} + bool pci_device_iommu_support_va(const struct rte_pci_device *dev) { @@ -501,6 +533,16 @@ pci_device_iommu_support_va(const struct rte_pci_device *dev) char filename[PATH_MAX]; FILE *fp; uint64_t mgaw, vtd_cap_reg = 0; + struct stat s; + + if (stat("/sys/class/iommu/ivhd2/amd-iommu", &s) == 0) { + mgaw = pci_device_amd_iommu_support_va(addr); + if (mgaw > 0) { + rte_mem_set_dma_mask(mgaw); + return true; + } + return false; + } snprintf(filename, sizeof(filename), "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap", -- 2.34.1