From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 40AF6A0032; Wed, 14 Sep 2022 07:09:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4F3D742802; Wed, 14 Sep 2022 07:09:06 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id E211E40E50 for ; Wed, 14 Sep 2022 07:09:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663132144; x=1694668144; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PjQ+ikNOEbXxCahYTaxey2C1bisMM2EmSzql4Rx9vh0=; b=RWGBwMUeZ4VorQP4jTx5zixq965Ci/YYoGOFd9tgzv3Y5vW2P9LJsals LYysqmCJV3VvF/8ta1w3idGKAbZgSwQoYgJhNpEzBrcRVDKcg0S2eVUsl jqMVPienK/aIIHIzH2f+EpiaOtjWQgc9ex5rWafs6G0toRfXulnK0vTwh r87koDvRXKWDWCVmrfpZAZQaiEZag3DCDMGrp0IakmKoZIu8Fh9aqwIiM mZi2Wp132+0T4RpMCCVk6GBzih4gosVSzVdNb1QqrghWVSsIIvo4J7c0N 34hFy6cheCCIHR+qlu0ekIj65pHG/FxzX8Fv28SR8nvsWolbpN1crE+MF g==; X-IronPort-AV: E=McAfee;i="6500,9779,10469"; a="298336393" X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="298336393" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2022 22:09:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="945369017" Received: from txandevlnx322.an.intel.com ([10.123.117.44]) by fmsmga005.fm.intel.com with ESMTP; 13 Sep 2022 22:09:02 -0700 From: Naga Harish K S V To: jerinj@marvell.com Cc: dev@dpdk.org, erik.g.carrillo@intel.com, pbhagavatula@marvell.com, sthotton@marvell.com Subject: [PATCH v5 3/4] test/event: update periodic event timer tests Date: Wed, 14 Sep 2022 00:08:53 -0500 Message-Id: <20220914050855.1677489-3-s.v.naga.harish.k@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20220914050855.1677489-1-s.v.naga.harish.k@intel.com> References: <20220812160714.287055-1-s.v.naga.harish.k@intel.com> <20220914050855.1677489-1-s.v.naga.harish.k@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch updates the software timer adapter tests to configure and use periodic event timers. Signed-off-by: Naga Harish K S V --- app/test/test_event_timer_adapter.c | 41 ++++++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/app/test/test_event_timer_adapter.c b/app/test/test_event_timer_adapter.c index d6170bb589..654c412836 100644 --- a/app/test/test_event_timer_adapter.c +++ b/app/test/test_event_timer_adapter.c @@ -386,11 +386,22 @@ timdev_setup_msec(void) static int timdev_setup_msec_periodic(void) { + uint32_t caps = 0; + uint64_t max_tmo_ns; + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES | RTE_EVENT_TIMER_ADAPTER_F_PERIODIC; + TEST_ASSERT_SUCCESS(rte_event_timer_adapter_caps_get(evdev, &caps), + "failed to get adapter capabilities"); + + if (caps & RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT) + max_tmo_ns = 0; + else + max_tmo_ns = 180 * NSECPERSEC; + /* Periodic mode with 100 ms resolution */ - return _timdev_setup(0, NSECPERSEC / 10, flags); + return _timdev_setup(max_tmo_ns, NSECPERSEC / 10, flags); } static int @@ -409,7 +420,7 @@ timdev_setup_sec_periodic(void) RTE_EVENT_TIMER_ADAPTER_F_PERIODIC; /* Periodic mode with 1 sec resolution */ - return _timdev_setup(0, NSECPERSEC, flags); + return _timdev_setup(180 * NSECPERSEC, NSECPERSEC, flags); } static int @@ -561,12 +572,23 @@ test_timer_arm(void) static inline int test_timer_arm_periodic(void) { + uint32_t caps = 0; + uint32_t timeout_count = 0; + TEST_ASSERT_SUCCESS(_arm_timers(1, MAX_TIMERS), "Failed to arm timers"); /* With a resolution of 100ms and wait time of 1sec, * there will be 10 * MAX_TIMERS periodic timer triggers. */ - TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, 10 * MAX_TIMERS, 0), + TEST_ASSERT_SUCCESS(rte_event_timer_adapter_caps_get(evdev, &caps), + "failed to get adapter capabilities"); + + if (caps & RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT) + timeout_count = 10; + else + timeout_count = 9; + + TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, timeout_count * MAX_TIMERS, 0), "Timer triggered count doesn't match arm count"); return TEST_SUCCESS; } @@ -649,12 +671,23 @@ test_timer_arm_burst(void) static inline int test_timer_arm_burst_periodic(void) { + uint32_t caps = 0; + uint32_t timeout_count = 0; + TEST_ASSERT_SUCCESS(_arm_timers_burst(1, MAX_TIMERS), "Failed to arm timers"); /* With a resolution of 100ms and wait time of 1sec, * there will be 10 * MAX_TIMERS periodic timer triggers. */ - TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, 10 * MAX_TIMERS, 0), + TEST_ASSERT_SUCCESS(rte_event_timer_adapter_caps_get(evdev, &caps), + "failed to get adapter capabilities"); + + if (caps & RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT) + timeout_count = 10; + else + timeout_count = 9; + + TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, timeout_count * MAX_TIMERS, 0), "Timer triggered count doesn't match arm count"); return TEST_SUCCESS; -- 2.25.1