From: Alex Vesker <valex@nvidia.com>
To: <valex@nvidia.com>, <viacheslavo@nvidia.com>, <erezsh@nvidia.com>,
<thomas@monjalon.net>, <suanmingm@nvidia.com>,
Matan Azrad <matan@nvidia.com>
Cc: <dev@dpdk.org>, <orika@nvidia.com>
Subject: [v1 14/19] net/mlx5/hws: Add HWS table object
Date: Thu, 22 Sep 2022 22:03:39 +0300 [thread overview]
Message-ID: <20220922190345.394-15-valex@nvidia.com> (raw)
In-Reply-To: <20220922190345.394-1-valex@nvidia.com>
HWS table resides under the context object, each context can
have multiple tables with different steering types RX/TX/FDB.
The table is not only a logical object but it is also represented
in the HW, packets can be steered to the table and from there
to other tables.
Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Signed-off-by: Alex Vesker <valex@nvidia.com>
---
drivers/net/mlx5/hws/mlx5dr_table.c | 248 ++++++++++++++++++++++++++++
drivers/net/mlx5/hws/mlx5dr_table.h | 44 +++++
2 files changed, 292 insertions(+)
create mode 100644 drivers/net/mlx5/hws/mlx5dr_table.c
create mode 100644 drivers/net/mlx5/hws/mlx5dr_table.h
diff --git a/drivers/net/mlx5/hws/mlx5dr_table.c b/drivers/net/mlx5/hws/mlx5dr_table.c
new file mode 100644
index 0000000000..171c244491
--- /dev/null
+++ b/drivers/net/mlx5/hws/mlx5dr_table.c
@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) Copyright (c) 2022 NVIDIA Corporation 2021 NVIDIA CORPORATION. All rights reserved. Affiliates
+ */
+
+#include "mlx5dr_internal.h"
+
+static void mlx5dr_table_init_next_ft_attr(struct mlx5dr_table *tbl,
+ struct mlx5dr_cmd_ft_create_attr *ft_attr)
+{
+ ft_attr->type = tbl->fw_ft_type;
+ if (tbl->type == MLX5DR_TABLE_TYPE_FDB)
+ ft_attr->level = tbl->ctx->caps->fdb_ft.max_level - 1;
+ else
+ ft_attr->level = tbl->ctx->caps->nic_ft.max_level - 1;
+ ft_attr->rtc_valid = true;
+}
+
+/* call this under ctx->ctrl_lock */
+static int
+mlx5dr_table_up_default_fdb_miss_tbl(struct mlx5dr_table *tbl)
+{
+ struct mlx5dr_cmd_ft_create_attr ft_attr = {0};
+ struct mlx5dr_cmd_forward_tbl *default_miss;
+ struct mlx5dr_context *ctx = tbl->ctx;
+ uint8_t tbl_type = tbl->type;
+ uint32_t vport;
+
+ if (tbl->type != MLX5DR_TABLE_TYPE_FDB)
+ return 0;
+
+ if (ctx->common_res[tbl_type].default_miss) {
+ ctx->common_res[tbl_type].default_miss->refcount++;
+ return 0;
+ }
+
+ ft_attr.type = tbl->fw_ft_type;
+ ft_attr.level = tbl->ctx->caps->fdb_ft.max_level; /* The last level */
+ ft_attr.rtc_valid = false;
+
+ assert(ctx->caps->eswitch_manager);
+ vport = ctx->caps->eswitch_manager_vport_number;
+
+ default_miss = mlx5dr_cmd_miss_ft_create(ctx->ibv_ctx, &ft_attr, vport);
+ if (!default_miss) {
+ DR_LOG(ERR, "Failed to default miss table type: 0x%x", tbl_type);
+ return rte_errno;
+ }
+
+ ctx->common_res[tbl_type].default_miss = default_miss;
+ ctx->common_res[tbl_type].default_miss->refcount++;
+ return 0;
+}
+
+/* called under pthread_spin_lock(&ctx->ctrl_lock) */
+static void mlx5dr_table_down_default_fdb_miss_tbl(struct mlx5dr_table *tbl)
+{
+ struct mlx5dr_cmd_forward_tbl *default_miss;
+ struct mlx5dr_context *ctx = tbl->ctx;
+ uint8_t tbl_type = tbl->type;
+
+ if (tbl->type != MLX5DR_TABLE_TYPE_FDB)
+ return;
+
+ default_miss = ctx->common_res[tbl_type].default_miss;
+ if (--default_miss->refcount)
+ return;
+
+ mlx5dr_cmd_miss_ft_destroy(default_miss);
+
+ simple_free(default_miss);
+ ctx->common_res[tbl_type].default_miss = NULL;
+}
+
+static int
+mlx5dr_table_connect_to_default_miss_tbl(struct mlx5dr_table *tbl,
+ struct mlx5dr_devx_obj *ft)
+{
+ struct mlx5dr_cmd_ft_modify_attr ft_attr = {0};
+ int ret;
+
+ assert(tbl->type == MLX5DR_TABLE_TYPE_FDB);
+
+ mlx5dr_cmd_set_attr_connect_miss_tbl(tbl->ctx,
+ tbl->fw_ft_type,
+ tbl->type,
+ &ft_attr);
+
+ /* Connect to next */
+ ret = mlx5dr_cmd_flow_table_modify(ft, &ft_attr);
+ if (ret) {
+ DR_LOG(ERR, "Failed to connect FT to default FDB FT");
+ return errno;
+ }
+
+ return 0;
+}
+
+struct mlx5dr_devx_obj *
+mlx5dr_table_create_default_ft(struct mlx5dr_table *tbl)
+{
+ struct mlx5dr_cmd_ft_create_attr ft_attr = {0};
+ struct mlx5dr_devx_obj *ft_obj;
+ int ret;
+
+ mlx5dr_table_init_next_ft_attr(tbl, &ft_attr);
+
+ ft_obj = mlx5dr_cmd_flow_table_create(tbl->ctx->ibv_ctx, &ft_attr);
+ if (ft_obj && tbl->type == MLX5DR_TABLE_TYPE_FDB) {
+ /* take/create ref over the default miss */
+ ret = mlx5dr_table_up_default_fdb_miss_tbl(tbl);
+ if (ret) {
+ DR_LOG(ERR, "Failed to get default fdb miss");
+ goto free_ft_obj;
+ }
+ ret = mlx5dr_table_connect_to_default_miss_tbl(tbl, ft_obj);
+ if (ret) {
+ DR_LOG(ERR, "Failed connecting to default miss tbl");
+ goto down_miss_tbl;
+ }
+ }
+
+ return ft_obj;
+
+down_miss_tbl:
+ mlx5dr_table_down_default_fdb_miss_tbl(tbl);
+free_ft_obj:
+ mlx5dr_cmd_destroy_obj(ft_obj);
+ return NULL;
+}
+
+void mlx5dr_table_destroy_default_ft(struct mlx5dr_table *tbl,
+ struct mlx5dr_devx_obj *ft_obj)
+{
+ mlx5dr_table_down_default_fdb_miss_tbl(tbl);
+ mlx5dr_cmd_destroy_obj(ft_obj);
+}
+
+static int mlx5dr_table_init(struct mlx5dr_table *tbl)
+{
+ struct mlx5dr_context *ctx = tbl->ctx;
+ int ret;
+
+ if (mlx5dr_table_is_root(tbl))
+ return 0;
+
+ if (!(tbl->ctx->flags & MLX5DR_CONTEXT_FLAG_HWS_SUPPORT)) {
+ DR_LOG(ERR, "HWS not supported, cannot create mlx5dr_table");
+ rte_errno = EOPNOTSUPP;
+ return rte_errno;
+ }
+
+ switch (tbl->type) {
+ case MLX5DR_TABLE_TYPE_NIC_RX:
+ tbl->fw_ft_type = FS_FT_NIC_RX;
+ break;
+ case MLX5DR_TABLE_TYPE_NIC_TX:
+ tbl->fw_ft_type = FS_FT_NIC_TX;
+ break;
+ case MLX5DR_TABLE_TYPE_FDB:
+ tbl->fw_ft_type = FS_FT_FDB;
+ break;
+ default:
+ assert(0);
+ break;
+ }
+
+ pthread_spin_lock(&ctx->ctrl_lock);
+ tbl->ft = mlx5dr_table_create_default_ft(tbl);
+ if (!tbl->ft) {
+ DR_LOG(ERR, "Failed to create flow table devx object");
+ pthread_spin_unlock(&ctx->ctrl_lock);
+ return rte_errno;
+ }
+
+ ret = mlx5dr_action_get_default_stc(ctx, tbl->type);
+ if (ret)
+ goto tbl_destroy;
+ pthread_spin_unlock(&ctx->ctrl_lock);
+
+ return 0;
+
+tbl_destroy:
+ mlx5dr_table_destroy_default_ft(tbl, tbl->ft);
+ pthread_spin_unlock(&ctx->ctrl_lock);
+ return rte_errno;
+}
+
+static void mlx5dr_table_uninit(struct mlx5dr_table *tbl)
+{
+ if (mlx5dr_table_is_root(tbl))
+ return;
+ pthread_spin_lock(&tbl->ctx->ctrl_lock);
+ mlx5dr_action_put_default_stc(tbl->ctx, tbl->type);
+ mlx5dr_table_destroy_default_ft(tbl, tbl->ft);
+ pthread_spin_unlock(&tbl->ctx->ctrl_lock);
+}
+
+struct mlx5dr_table *mlx5dr_table_create(struct mlx5dr_context *ctx,
+ struct mlx5dr_table_attr *attr)
+{
+ struct mlx5dr_table *tbl;
+ int ret;
+
+ if (attr->type > MLX5DR_TABLE_TYPE_FDB) {
+ DR_LOG(ERR, "Invalid table type %d", attr->type);
+ return NULL;
+ }
+
+ tbl = simple_malloc(sizeof(*tbl));
+ if (!tbl) {
+ rte_errno = ENOMEM;
+ return NULL;
+ }
+
+ tbl->ctx = ctx;
+ tbl->type = attr->type;
+ tbl->level = attr->level;
+ LIST_INIT(&tbl->head);
+
+ ret = mlx5dr_table_init(tbl);
+ if (ret) {
+ DR_LOG(ERR, "Failed to initialise table");
+ goto free_tbl;
+ }
+
+ pthread_spin_lock(&ctx->ctrl_lock);
+ LIST_INSERT_HEAD(&ctx->head, tbl, next);
+ pthread_spin_unlock(&ctx->ctrl_lock);
+
+ return tbl;
+
+free_tbl:
+ simple_free(tbl);
+ return NULL;
+}
+
+int mlx5dr_table_destroy(struct mlx5dr_table *tbl)
+{
+ struct mlx5dr_context *ctx = tbl->ctx;
+
+ pthread_spin_lock(&ctx->ctrl_lock);
+ LIST_REMOVE(tbl, next);
+ pthread_spin_unlock(&ctx->ctrl_lock);
+ mlx5dr_table_uninit(tbl);
+ simple_free(tbl);
+
+ return 0;
+}
diff --git a/drivers/net/mlx5/hws/mlx5dr_table.h b/drivers/net/mlx5/hws/mlx5dr_table.h
new file mode 100644
index 0000000000..b0c39b0e69
--- /dev/null
+++ b/drivers/net/mlx5/hws/mlx5dr_table.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) Copyright (c) 2022 NVIDIA Corporation 2021 NVIDIA CORPORATION. All rights reserved. Affiliates
+ */
+
+#ifndef MLX5DR_TABLE_H_
+#define MLX5DR_TABLE_H_
+
+#define MLX5DR_ROOT_LEVEL 0
+
+struct mlx5dr_table {
+ struct mlx5dr_context *ctx;
+ struct mlx5dr_devx_obj *ft;
+ enum mlx5dr_table_type type;
+ uint32_t fw_ft_type;
+ uint32_t level;
+ LIST_HEAD(matcher_head, mlx5dr_matcher) head;
+ LIST_ENTRY(mlx5dr_table) next;
+};
+
+static inline
+uint32_t mlx5dr_table_get_res_fw_ft_type(enum mlx5dr_table_type tbl_type,
+ bool is_mirror)
+{
+ if (tbl_type == MLX5DR_TABLE_TYPE_NIC_RX)
+ return FS_FT_NIC_RX;
+ else if (tbl_type == MLX5DR_TABLE_TYPE_NIC_TX)
+ return FS_FT_NIC_TX;
+ else if (tbl_type == MLX5DR_TABLE_TYPE_FDB)
+ return is_mirror ? FS_FT_FDB_TX : FS_FT_FDB_RX;
+
+ assert(0);
+ return 0;
+}
+
+static inline bool mlx5dr_table_is_root(struct mlx5dr_table *tbl)
+{
+ return (tbl->level == MLX5DR_ROOT_LEVEL);
+}
+
+struct mlx5dr_devx_obj *mlx5dr_table_create_default_ft(struct mlx5dr_table *tbl);
+
+void mlx5dr_table_destroy_default_ft(struct mlx5dr_table *tbl,
+ struct mlx5dr_devx_obj *ft_obj);
+#endif
--
2.18.1
next prev parent reply other threads:[~2022-09-22 19:06 UTC|newest]
Thread overview: 134+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-22 19:03 [v1 00/19] net/mlx5: Add HW steering low level support Alex Vesker
2022-09-22 19:03 ` [v1 01/19] net/mlx5: split flow item translation Alex Vesker
2022-09-22 19:03 ` [v1 02/19] net/mlx5: split flow item matcher and value translation Alex Vesker
2022-09-22 19:03 ` [v1 03/19] net/mlx5: add hardware steering item translation function Alex Vesker
2022-09-22 19:03 ` [v1 04/19] net/mlx5: add port to metadata conversion Alex Vesker
2022-09-22 19:03 ` [v1 05/19] common/mlx5: query set capability of registers Alex Vesker
2022-09-22 19:03 ` [v1 06/19] net/mlx5: provide the available tag registers Alex Vesker
2022-09-22 19:03 ` [v1 07/19] net/mlx5: Add additional glue functions for HWS Alex Vesker
2022-09-22 19:03 ` [v1 08/19] net/mlx5: Remove stub HWS support Alex Vesker
2022-09-22 19:03 ` [v1 09/19] net/mlx5/hws: Add HWS command layer Alex Vesker
2022-09-22 19:03 ` [v1 10/19] net/mlx5/hws: Add HWS pool and buddy Alex Vesker
2022-09-22 19:03 ` [v1 11/19] net/mlx5/hws: Add HWS send layer Alex Vesker
2022-09-22 19:03 ` [v1 12/19] net/mlx5/hws: Add HWS definer layer Alex Vesker
2022-09-22 19:03 ` [v1 13/19] net/mlx5/hws: Add HWS context object Alex Vesker
2022-09-22 19:03 ` Alex Vesker [this message]
2022-09-22 19:03 ` [v1 15/19] net/mlx5/hws: Add HWS matcher object Alex Vesker
2022-09-22 19:03 ` [v1 16/19] net/mlx5/hws: Add HWS rule object Alex Vesker
2022-09-22 19:03 ` [v1 17/19] net/mlx5/hws: Add HWS action object Alex Vesker
2022-09-22 19:03 ` [v1 18/19] net/mlx5/hws: Add HWS debug layer Alex Vesker
2022-09-22 19:03 ` [v1 19/19] net/mlx5/hws: Enable HWS Alex Vesker
2022-10-06 15:03 ` [v2 00/19] net/mlx5: Add HW steering low level support Alex Vesker
2022-10-06 15:03 ` [v2 01/19] net/mlx5: split flow item translation Alex Vesker
2022-10-06 15:03 ` [v2 02/19] net/mlx5: split flow item matcher and value translation Alex Vesker
2022-10-06 15:03 ` [v2 03/19] net/mlx5: add hardware steering item translation function Alex Vesker
2022-10-06 15:03 ` [v2 04/19] net/mlx5: add port to metadata conversion Alex Vesker
2022-10-06 15:03 ` [v2 05/19] common/mlx5: query set capability of registers Alex Vesker
2022-10-06 15:03 ` [v2 06/19] net/mlx5: provide the available tag registers Alex Vesker
2022-10-06 15:03 ` [v2 07/19] net/mlx5: Add additional glue functions for HWS Alex Vesker
2022-10-06 15:03 ` [v2 08/19] net/mlx5: Remove stub HWS support Alex Vesker
2022-10-06 15:03 ` [v2 09/19] net/mlx5/hws: Add HWS command layer Alex Vesker
2022-10-06 15:03 ` [v2 10/19] net/mlx5/hws: Add HWS pool and buddy Alex Vesker
2022-10-06 15:03 ` [v2 11/19] net/mlx5/hws: Add HWS send layer Alex Vesker
2022-10-06 15:03 ` [v2 12/19] net/mlx5/hws: Add HWS definer layer Alex Vesker
2022-10-06 15:03 ` [v2 13/19] net/mlx5/hws: Add HWS context object Alex Vesker
2022-10-06 15:03 ` [v2 14/19] net/mlx5/hws: Add HWS table object Alex Vesker
2022-10-06 15:03 ` [v2 15/19] net/mlx5/hws: Add HWS matcher object Alex Vesker
2022-10-06 15:03 ` [v2 16/19] net/mlx5/hws: Add HWS rule object Alex Vesker
2022-10-06 15:03 ` [v2 17/19] net/mlx5/hws: Add HWS action object Alex Vesker
2022-10-06 15:03 ` [v2 18/19] net/mlx5/hws: Add HWS debug layer Alex Vesker
2022-10-06 15:03 ` [v2 19/19] net/mlx5/hws: Enable HWS Alex Vesker
2022-10-14 11:48 ` [v3 00/18] net/mlx5: Add HW steering low level support Alex Vesker
2022-10-14 11:48 ` [v3 01/18] net/mlx5: split flow item translation Alex Vesker
2022-10-14 11:48 ` [v3 02/18] net/mlx5: split flow item matcher and value translation Alex Vesker
2022-10-14 11:48 ` [v3 03/18] net/mlx5: add hardware steering item translation function Alex Vesker
2022-10-14 11:48 ` [v3 04/18] net/mlx5: add port to metadata conversion Alex Vesker
2022-10-14 11:48 ` [v3 05/18] common/mlx5: query set capability of registers Alex Vesker
2022-10-14 11:48 ` [v3 06/18] net/mlx5: provide the available tag registers Alex Vesker
2022-10-14 11:48 ` [v3 07/18] net/mlx5: Add additional glue functions for HWS Alex Vesker
2022-10-14 11:48 ` [v3 08/18] net/mlx5/hws: Add HWS command layer Alex Vesker
2022-10-14 11:48 ` [v3 09/18] net/mlx5/hws: Add HWS pool and buddy Alex Vesker
2022-10-14 11:48 ` [v3 10/18] net/mlx5/hws: Add HWS send layer Alex Vesker
2022-10-14 11:48 ` [v3 11/18] net/mlx5/hws: Add HWS definer layer Alex Vesker
2022-10-14 11:48 ` [v3 12/18] net/mlx5/hws: Add HWS context object Alex Vesker
2022-10-14 11:48 ` [v3 13/18] net/mlx5/hws: Add HWS table object Alex Vesker
2022-10-14 11:48 ` [v3 14/18] net/mlx5/hws: Add HWS matcher object Alex Vesker
2022-10-14 11:48 ` [v3 15/18] net/mlx5/hws: Add HWS rule object Alex Vesker
2022-10-14 11:48 ` [v3 16/18] net/mlx5/hws: Add HWS action object Alex Vesker
2022-10-14 11:48 ` [v3 17/18] net/mlx5/hws: Add HWS debug layer Alex Vesker
2022-10-14 11:48 ` [v3 18/18] net/mlx5/hws: Enable HWS Alex Vesker
2022-10-19 14:42 ` [v4 00/18] net/mlx5: Add HW steering low level support Alex Vesker
2022-10-19 14:42 ` [v4 01/18] net/mlx5: split flow item translation Alex Vesker
2022-10-19 14:42 ` [v4 02/18] net/mlx5: split flow item matcher and value translation Alex Vesker
2022-10-19 14:42 ` [v4 03/18] net/mlx5: add hardware steering item translation function Alex Vesker
2022-10-19 14:42 ` [v4 04/18] net/mlx5: add port to metadata conversion Alex Vesker
2022-10-19 14:42 ` [v4 05/18] common/mlx5: query set capability of registers Alex Vesker
2022-10-19 14:42 ` [v4 06/18] net/mlx5: provide the available tag registers Alex Vesker
2022-10-19 14:42 ` [v4 07/18] net/mlx5: Add additional glue functions for HWS Alex Vesker
2022-10-19 14:42 ` [v4 08/18] net/mlx5/hws: Add HWS command layer Alex Vesker
2022-10-19 14:42 ` [v4 09/18] net/mlx5/hws: Add HWS pool and buddy Alex Vesker
2022-10-19 14:42 ` [v4 10/18] net/mlx5/hws: Add HWS send layer Alex Vesker
2022-10-19 14:42 ` [v4 11/18] net/mlx5/hws: Add HWS definer layer Alex Vesker
2022-10-19 14:42 ` [v4 12/18] net/mlx5/hws: Add HWS context object Alex Vesker
2022-10-19 14:42 ` [v4 13/18] net/mlx5/hws: Add HWS table object Alex Vesker
2022-10-19 14:42 ` [v4 14/18] net/mlx5/hws: Add HWS matcher object Alex Vesker
2022-10-19 14:42 ` [v4 15/18] net/mlx5/hws: Add HWS rule object Alex Vesker
2022-10-19 14:42 ` [v4 16/18] net/mlx5/hws: Add HWS action object Alex Vesker
2022-10-19 14:42 ` [v4 17/18] net/mlx5/hws: Add HWS debug layer Alex Vesker
2022-10-19 14:42 ` [v4 18/18] net/mlx5/hws: Enable HWS Alex Vesker
2022-10-19 20:57 ` [v5 00/18] net/mlx5: Add HW steering low level support Alex Vesker
2022-10-19 20:57 ` [v5 01/18] net/mlx5: split flow item translation Alex Vesker
2022-10-19 20:57 ` [v5 02/18] net/mlx5: split flow item matcher and value translation Alex Vesker
2022-10-19 20:57 ` [v5 03/18] net/mlx5: add hardware steering item translation function Alex Vesker
2022-10-19 20:57 ` [v5 04/18] net/mlx5: add port to metadata conversion Alex Vesker
2022-10-19 20:57 ` [v5 05/18] common/mlx5: query set capability of registers Alex Vesker
2022-10-19 20:57 ` [v5 06/18] net/mlx5: provide the available tag registers Alex Vesker
2022-10-19 20:57 ` [v5 07/18] net/mlx5: Add additional glue functions for HWS Alex Vesker
2022-10-19 20:57 ` [v5 08/18] net/mlx5/hws: Add HWS command layer Alex Vesker
2022-10-19 20:57 ` [v5 09/18] net/mlx5/hws: Add HWS pool and buddy Alex Vesker
2022-10-19 20:57 ` [v5 10/18] net/mlx5/hws: Add HWS send layer Alex Vesker
2022-10-19 20:57 ` [v5 11/18] net/mlx5/hws: Add HWS definer layer Alex Vesker
2022-10-19 20:57 ` [v5 12/18] net/mlx5/hws: Add HWS context object Alex Vesker
2022-10-19 20:57 ` [v5 13/18] net/mlx5/hws: Add HWS table object Alex Vesker
2022-10-19 20:57 ` [v5 14/18] net/mlx5/hws: Add HWS matcher object Alex Vesker
2022-10-19 20:57 ` [v5 15/18] net/mlx5/hws: Add HWS rule object Alex Vesker
2022-10-19 20:57 ` [v5 16/18] net/mlx5/hws: Add HWS action object Alex Vesker
2022-10-19 20:57 ` [v5 17/18] net/mlx5/hws: Add HWS debug layer Alex Vesker
2022-10-19 20:57 ` [v5 18/18] net/mlx5/hws: Enable HWS Alex Vesker
2022-10-20 15:57 ` [v6 00/18] net/mlx5: Add HW steering low level support Alex Vesker
2022-10-20 15:57 ` [v6 01/18] net/mlx5: split flow item translation Alex Vesker
2022-10-24 6:47 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 02/18] net/mlx5: split flow item matcher and value translation Alex Vesker
2022-10-24 6:49 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 03/18] net/mlx5: add hardware steering item translation function Alex Vesker
2022-10-24 6:50 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 04/18] net/mlx5: add port to metadata conversion Alex Vesker
2022-10-24 6:50 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 05/18] common/mlx5: query set capability of registers Alex Vesker
2022-10-24 6:50 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 06/18] net/mlx5: provide the available tag registers Alex Vesker
2022-10-24 6:51 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 07/18] net/mlx5: Add additional glue functions for HWS Alex Vesker
2022-10-24 6:52 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 08/18] net/mlx5/hws: Add HWS command layer Alex Vesker
2022-10-24 6:52 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 09/18] net/mlx5/hws: Add HWS pool and buddy Alex Vesker
2022-10-24 6:52 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 10/18] net/mlx5/hws: Add HWS send layer Alex Vesker
2022-10-24 6:53 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 11/18] net/mlx5/hws: Add HWS definer layer Alex Vesker
2022-10-24 6:53 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 12/18] net/mlx5/hws: Add HWS context object Alex Vesker
2022-10-24 6:53 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 13/18] net/mlx5/hws: Add HWS table object Alex Vesker
2022-10-24 6:54 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 14/18] net/mlx5/hws: Add HWS matcher object Alex Vesker
2022-10-24 6:54 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 15/18] net/mlx5/hws: Add HWS rule object Alex Vesker
2022-10-24 6:54 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 16/18] net/mlx5/hws: Add HWS action object Alex Vesker
2022-10-20 15:57 ` [v6 17/18] net/mlx5/hws: Add HWS debug layer Alex Vesker
2022-10-24 6:54 ` Slava Ovsiienko
2022-10-20 15:57 ` [v6 18/18] net/mlx5/hws: Enable HWS Alex Vesker
2022-10-24 6:54 ` Slava Ovsiienko
2022-10-24 10:56 ` [v6 00/18] net/mlx5: Add HW steering low level support Raslan Darawsheh
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