From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 17DE8A054A; Fri, 23 Sep 2022 16:46:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 436FD42C18; Fri, 23 Sep 2022 16:44:41 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by mails.dpdk.org (Postfix) with ESMTP id C55B342C0D for ; Fri, 23 Sep 2022 16:44:39 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Px3dKEugVBaeOSSBBrHwyqq8jyFdMIVc5xquEhUAYEZ4/4Hm9g5rREQOYEfM+ZManmRZcN6e7EJWlX7SgawGRNbllrHWNdkhw89sTKymNnI4RTyJqQnX76nLRP11s5CMrdFA/14a9ubBI7U9un8qoFBB1TDm6ZwlfxHRwYLEdx0aT5NeMvpFcu6VePQOA/7Da/HLr2wAoSYBl6fzVQOU3sT66REOgGbmlJ27v1I4Eigh6G7h4EDOih2VTqgDNdWHtBfEwlYGyDuInMTzqq06Kn5jhDNgiFQXXQxfci/igmfTQ7l0k4eqd2xIBqzgM+lTS+QeIn4aFbKtvXOUSW4HMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=F71ghNs8KQUyvk7+8WEoACTT34XlaLCOz0GVovVyO3g=; b=WOqFWZ7urkIDj78dnTzUvqwkFyFpTTixlPV9SKzhTciosTWKT/fZJTve/A0VKdaHUeZTy5+BhETVqe+vSYtEhcrTeAjCAOiWQ8pxa5pSMaYY+qCDwcjgy58WpVRe5209EQB3hbvtTyLqeaeTkPN6SDxRKRCdF0Uf3jzaIl9tc/LkjIp2ZRbCfBZntTznwM982rhAdn/r4IwHikAo3PJy+QdRjAegz2dWOA/80ouJHmaNd7zZNNC0mpTodUkW5PN9HrSDnSu12/LKAjAgBTlB4caap1PZGqfHJKSurN27ujjkH4+xeaCOGAKnP2GB/AkOFYEVyi7MeM5mxWIohnqQow== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=F71ghNs8KQUyvk7+8WEoACTT34XlaLCOz0GVovVyO3g=; b=bPAKxlbnTmYPCt7tMNXF0b17MLT5YXIvTcUbzwrAQW0712KIW1ryRvL3Xt6ZBqUk5XXQDBmd3MneQw9sp4t9YLARDLkBaePIu+FcCzZFkjYrvTw7A8jwoyOsQ3M92Lts94SUX2OPqIdlKWJZRLbi+STXYnHyfH1Au+6VaEZBzbvqgA+HN/qsip4F4edVaP9nUeDGg9WI9uxzOYZc4lKr0PlTTblqvjc1EEhbH37rbGBME1/YZq/osVw+P5BoZcavyvlPlwzrqcCpC4yxgrzwbqADeZV4k7jzj71pLRr/zkf2pa06HTy0sXTD8w2QqFT3Cj/eUxHqmZVGy6gIFx34Qg== Received: from MW4PR03CA0227.namprd03.prod.outlook.com (2603:10b6:303:b9::22) by CH2PR12MB4071.namprd12.prod.outlook.com (2603:10b6:610:7b::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.20; Fri, 23 Sep 2022 14:44:37 +0000 Received: from CO1NAM11FT026.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b9:cafe::a8) by MW4PR03CA0227.outlook.office365.com (2603:10b6:303:b9::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.20 via Frontend Transport; Fri, 23 Sep 2022 14:44:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1NAM11FT026.mail.protection.outlook.com (10.13.175.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.14 via Frontend Transport; Fri, 23 Sep 2022 14:44:37 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 23 Sep 2022 07:44:19 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 23 Sep 2022 07:44:18 -0700 From: Suanming Mou To: Matan Azrad , Viacheslav Ovsiienko CC: , Dariusz Sosnowski Subject: [PATCH 17/27] net/mlx5: add pattern and table attribute validation Date: Fri, 23 Sep 2022 17:43:24 +0300 Message-ID: <20220923144334.27736-18-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20220923144334.27736-1-suanmingm@nvidia.com> References: <20220923144334.27736-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT026:EE_|CH2PR12MB4071:EE_ X-MS-Office365-Filtering-Correlation-Id: 0824ef34-d9de-43ba-ae0c-08da9d7223be X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: X/ADU2shSYEHtVNEumEHvgFxgixBHaaWfjhk1XE0CFui5t/vXF6S2Z8JYegooETYRk7FE3zVd85XdlNUkSryBZ1mm6p55Xo0/tFxZdvNjW4NwdSYJtSKu+S/c/aneO8D0fCSAaRhUYbseJlnUTKfiLP9uk3uN6zKD4aEGUviRTD0YUnoWEtA5aUaFqvWVSJD/oXmCB4R5aNvVA7QP4DPCBoRCe38mkvlIemqknuElR1gpJqeJPmPfEcIx72PtReSoR8i3MEAAy0cqoSvl8kcP5g3hLvK9dloS2J/nYHqW38b85T3aYuhYIZXSAYUwiub0YuTGAtGBWK8qbf4tc5P8ua9FGr3KSv9pvRCok/f1P2aEnkCudyetjNgoBE/Byz4AI6vBE+pmHb7gXTjHZdg93x1nQd2Us4fmhBRtnDG4eLLjEE9IFhNJRUDOm9c1mflPz6VP3XuqJvQVk2FjlemNWISGcjRyhqxNfxDI2MUrd0DWz54CsrrOkqtN1tw74WA7T9/oPDPDZ9lhnb/ulWwWqNrXscF8YaqwgYaWqG3BRBNIVVyE1HCYoziJi2LWWmjG75nSuew/+W2HLmpokacWAUvouZ9BCaXmwKK0nOFCWxjGhEbvi8QfXATQohUrFuRu3Lr6LGeIVvfjEksN1peydw+xWmr8K7EmjC2ROfuJr+PtGkDWtwy7ipEVGPVzd2d8gU+x+qVSrU7nQFP2DY/bFdzmUi5DLxJZeTBWq9lNwUqv9bir/mBBmHQ3u8UGKd8BQD/ZuNyRN/6coyLtQ55xQ== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(376002)(136003)(396003)(39860400002)(346002)(451199015)(46966006)(36840700001)(40470700004)(36860700001)(26005)(6636002)(107886003)(36756003)(2906002)(7696005)(110136005)(54906003)(6666004)(2616005)(1076003)(16526019)(86362001)(186003)(4326008)(70586007)(70206006)(83380400001)(336012)(426003)(8676002)(55016003)(6286002)(316002)(41300700001)(40480700001)(47076005)(8936002)(5660300002)(7636003)(478600001)(40460700003)(82740400003)(82310400005)(356005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2022 14:44:37.6315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0824ef34-d9de-43ba-ae0c-08da9d7223be X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4071 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dariusz Sosnowski This patch adds validation of direction attributes of pattern templates and template tables. In case of pattern templates the following configurations are allowed (and if this configuration requires addition of implicit pattern items): 1. If E-Switch is enabled (i.e. dv_esw_en devarg is set to 1): 1. If a port is a VF/SF representor: 1. Ingress only - implicit pattern items are added. 2. Egress only - implicit pattern items are added. 2. If a port is a transfer proxy port (E-Switch Manager/PF representor): 1. Ingress, egress and transfer - no implicit items are added. This setting is useful for applications which require to receive traffic from devices connected to the E-Switch and did not hit any transfer flow rules. 2. Ingress only - implicit pattern items are added. 3. Egress only - implicit pattern items are added. 4. Transfer only - no implicit pattern items are added. 2. If E-Switch is disabled (i.e. dv_esw_en devarg is set to 0): 1. Ingress only - no implicit pattern items are added. 2. Egress only - no implicit pattern items are added. 3. Ingress and egress - no implicit pattern items are added. 4. Transfer is not allowed. In case of template tables, the table attributes must be consistent with attributes associated with pattern template attributes. Signed-off-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow_hw.c | 80 +++++++++++++++++++++++++-------- 1 file changed, 62 insertions(+), 18 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 92b61b63d1..dfbc434d54 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -2379,6 +2379,13 @@ flow_hw_table_create(struct rte_eth_dev *dev, for (i = 0; i < nb_item_templates; i++) { uint32_t ret; + if ((flow_attr.ingress && !item_templates[i]->attr.ingress) || + (flow_attr.egress && !item_templates[i]->attr.egress) || + (flow_attr.transfer && !item_templates[i]->attr.transfer)) { + DRV_LOG(ERR, "pattern template and template table attribute mismatch"); + rte_errno = EINVAL; + goto it_error; + } ret = __atomic_add_fetch(&item_templates[i]->refcnt, 1, __ATOMIC_RELAXED); if (ret <= 1) { @@ -2557,6 +2564,7 @@ flow_hw_template_table_create(struct rte_eth_dev *dev, uint8_t nb_action_templates, struct rte_flow_error *error) { + struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_flow_template_table_cfg cfg = { .attr = *attr, .external = true, @@ -2565,6 +2573,12 @@ flow_hw_template_table_create(struct rte_eth_dev *dev, if (flow_hw_translate_group(dev, &cfg, group, &cfg.attr.flow_attr.group, error)) return NULL; + if (priv->sh->config.dv_esw_en && cfg.attr.flow_attr.egress) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "egress flows are not supported with HW Steering" + " when E-Switch is enabled"); + return NULL; + } return flow_hw_table_create(dev, &cfg, item_templates, nb_item_templates, action_templates, nb_action_templates, error); } @@ -3254,11 +3268,48 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, const struct rte_flow_item items[], struct rte_flow_error *error) { + struct mlx5_priv *priv = dev->data->dev_private; int i; bool items_end = false; - RTE_SET_USED(dev); - RTE_SET_USED(attr); + if (!attr->ingress && !attr->egress && !attr->transfer) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "at least one of the direction attributes" + " must be specified"); + if (priv->sh->config.dv_esw_en) { + MLX5_ASSERT(priv->master || priv->representor); + if (priv->master) { + /* + * It is allowed to specify ingress, egress and transfer attributes + * at the same time, in order to construct flows catching all missed + * FDB traffic and forwarding it to the master port. + */ + if (!(attr->ingress ^ attr->egress ^ attr->transfer)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "only one or all direction attributes" + " at once can be used on transfer proxy" + " port"); + } else { + if (attr->transfer) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL, + "transfer attribute cannot be used with" + " port representors"); + if (attr->ingress && attr->egress) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "ingress and egress direction attributes" + " cannot be used at the same time on" + " port representors"); + } + } else { + if (attr->transfer) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL, + "transfer attribute cannot be used when" + " E-Switch is disabled"); + } for (i = 0; !items_end; i++) { int type = items[i].type; @@ -3289,7 +3340,15 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "Unsupported internal tag index"); + break; } + case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: + if (attr->ingress || attr->egress) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "represented port item cannot be used" + " when transfer attribute is set"); + break; case RTE_FLOW_ITEM_TYPE_VOID: case RTE_FLOW_ITEM_TYPE_ETH: case RTE_FLOW_ITEM_TYPE_VLAN: @@ -3299,7 +3358,6 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_TCP: case RTE_FLOW_ITEM_TYPE_GTP: case RTE_FLOW_ITEM_TYPE_GTP_PSC: - case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: case RTE_FLOW_ITEM_TYPE_VXLAN: case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE: case RTE_FLOW_ITEM_TYPE_META: @@ -3350,21 +3408,7 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, if (flow_hw_pattern_validate(dev, attr, items, error)) return NULL; - if (priv->sh->config.dv_esw_en && attr->ingress) { - /* - * Disallow pattern template with ingress and egress/transfer - * attributes in order to forbid implicit port matching - * on egress and transfer traffic. - */ - if (attr->egress || attr->transfer) { - rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, - "item template for ingress traffic" - " cannot be used for egress/transfer" - " traffic when E-Switch is enabled"); - return NULL; - } + if (priv->sh->config.dv_esw_en && attr->ingress && !attr->egress && !attr->transfer) { copied_items = flow_hw_copy_prepend_port_item(items, error); if (!copied_items) return NULL; -- 2.25.1