* [PATCH v7 0/7] Introduce support for LoongArch architecture
@ 2022-09-30 8:02 Min Zhou
2022-09-30 8:02 ` [PATCH v7 1/7] eal/loongarch: support " Min Zhou
` (8 more replies)
0 siblings, 9 replies; 20+ messages in thread
From: Min Zhou @ 2022-09-30 8:02 UTC (permalink / raw)
To: thomas, david.marchand, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev,
zhoumin
Cc: dev, maobibo
Dear team,
The following patch set is intended to support DPDK running on LoongArch
architecture.
LoongArch is the general processor architecture of Loongson Corporation
and is a new RISC ISA, which is a bit like MIPS or RISC-V.
The online documents of LoongArch architecture are here:
https://loongson.github.io/LoongArch-Documentation/README-EN.html
The latest build tools for LoongArch (binary) can be downloaded from:
https://github.com/loongson/build-tools
v7:
- rebase the patchset on the main repository
- add errno.h to rte_power_intrinsics.c according with
commit 72b452c5f259
v6:
- place some blocks for LoongArch in a pseudo alphabetical order
- remove some macros not used
- update release notes in the correct format
- remove some headers for LoongArch, including msclock, pflock and
ticketlock, which are now non-arch specific
- rename some helpers to make them more readable
- remove some copied comments
- force-set RTE_FORCE_INTRINSICS in config and remove non-arch
specific implementations
- fix format errors in meson file reported by check-meson.py
- rebase the patchset on the main repository
v5:
- merge all patches for supporting LoongArch EAL into one patch
- add LoongArch cross compilation document and update some documents
related to architecture
- remove vector stubs added for LoongArch in net/i40e and net/ixgbe
- add LOONGARCH64 cross compilation job in github ci
v4:
- rebase the patchset on the main repository of version 22.07.0
v3:
- add URL for cross compile tool chain
- remove rte_lpm_lsx.h which was a dummy vector implementation
because there is already a scalar implementation, thanks to
Michal Mazurek
- modify the name of compiler for cross compiling
- remove useless variable in meson.build
v2:
- use standard atomics of toolchain to implement
atomic operations
- implement spinlock based on standard atomics
Min Zhou (7):
eal/loongarch: support LoongArch architecture
net/ixgbe: add vector stubs for LoongArch
net/memif: set memfd syscall ID on LoongArch
net/tap: set BPF syscall ID for LoongArch
examples/l3fwd: enable LoongArch operation
test/cpuflags: add test for LoongArch cpu flag
ci: add LOONGARCH64 cross compilation job
.ci/linux-build.sh | 10 ++
.github/workflows/build.yml | 10 +-
MAINTAINERS | 6 ++
app/test/test_cpuflags.c | 41 ++++++++
app/test/test_xmmt_ops.h | 12 +++
.../loongarch/loongarch_loongarch64_linux_gcc | 16 ++++
config/loongarch/meson.build | 43 +++++++++
doc/guides/contributing/design.rst | 2 +-
.../cross_build_dpdk_for_loongarch.rst | 87 +++++++++++++++++
doc/guides/linux_gsg/index.rst | 1 +
doc/guides/nics/features.rst | 8 ++
doc/guides/nics/features/default.ini | 1 +
doc/guides/nics/features/ixgbe.ini | 1 +
doc/guides/rel_notes/release_22_11.rst | 7 ++
drivers/net/i40e/meson.build | 6 ++
drivers/net/ixgbe/ixgbe_rxtx.c | 7 +-
drivers/net/memif/rte_eth_memif.h | 2 +
drivers/net/tap/tap_bpf.h | 2 +
examples/l3fwd/l3fwd_em.c | 8 ++
lib/eal/linux/eal_memory.c | 4 +
lib/eal/loongarch/include/meson.build | 18 ++++
lib/eal/loongarch/include/rte_atomic.h | 47 ++++++++++
lib/eal/loongarch/include/rte_byteorder.h | 40 ++++++++
lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++
lib/eal/loongarch/include/rte_cycles.h | 47 ++++++++++
lib/eal/loongarch/include/rte_io.h | 18 ++++
lib/eal/loongarch/include/rte_memcpy.h | 61 ++++++++++++
lib/eal/loongarch/include/rte_pause.h | 24 +++++
.../loongarch/include/rte_power_intrinsics.h | 20 ++++
lib/eal/loongarch/include/rte_prefetch.h | 47 ++++++++++
lib/eal/loongarch/include/rte_rwlock.h | 42 +++++++++
lib/eal/loongarch/include/rte_spinlock.h | 64 +++++++++++++
lib/eal/loongarch/include/rte_vect.h | 65 +++++++++++++
lib/eal/loongarch/meson.build | 11 +++
lib/eal/loongarch/rte_cpuflags.c | 93 +++++++++++++++++++
lib/eal/loongarch/rte_cycles.c | 45 +++++++++
lib/eal/loongarch/rte_hypervisor.c | 11 +++
lib/eal/loongarch/rte_power_intrinsics.c | 53 +++++++++++
meson.build | 2 +
39 files changed, 1017 insertions(+), 4 deletions(-)
create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc
create mode 100644 config/loongarch/meson.build
create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
create mode 100644 lib/eal/loongarch/include/meson.build
create mode 100644 lib/eal/loongarch/include/rte_atomic.h
create mode 100644 lib/eal/loongarch/include/rte_byteorder.h
create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h
create mode 100644 lib/eal/loongarch/include/rte_cycles.h
create mode 100644 lib/eal/loongarch/include/rte_io.h
create mode 100644 lib/eal/loongarch/include/rte_memcpy.h
create mode 100644 lib/eal/loongarch/include/rte_pause.h
create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h
create mode 100644 lib/eal/loongarch/include/rte_prefetch.h
create mode 100644 lib/eal/loongarch/include/rte_rwlock.h
create mode 100644 lib/eal/loongarch/include/rte_spinlock.h
create mode 100644 lib/eal/loongarch/include/rte_vect.h
create mode 100644 lib/eal/loongarch/meson.build
create mode 100644 lib/eal/loongarch/rte_cpuflags.c
create mode 100644 lib/eal/loongarch/rte_cycles.c
create mode 100644 lib/eal/loongarch/rte_hypervisor.c
create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c
--
2.31.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v7 1/7] eal/loongarch: support LoongArch architecture 2022-09-30 8:02 [PATCH v7 0/7] Introduce support for LoongArch architecture Min Zhou @ 2022-09-30 8:02 ` Min Zhou 2022-10-03 17:15 ` David Marchand 2022-09-30 8:02 ` [PATCH v7 2/7] net/ixgbe: add vector stubs for LoongArch Min Zhou ` (7 subsequent siblings) 8 siblings, 1 reply; 20+ messages in thread From: Min Zhou @ 2022-09-30 8:02 UTC (permalink / raw) To: thomas, david.marchand, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, zhoumin Cc: dev, maobibo Add all necessary elements for DPDK to compile and run EAL on LoongArch64 Soc. This includes: - EAL library implementation for LoongArch ISA. - meson build structure for 'loongarch' architecture. RTE_ARCH_LOONGARCH define is added for architecture identification. - xmm_t structure operation stubs as there is no vector support in the current version for LoongArch. Compilation was tested on Debian and CentOS using loongarch64 cross-compile toolchain from x86 build hosts. Functions were tested on Loongnix and Kylin which are two Linux distributions supported LoongArch host based on Linux 4.19 maintained by Loongson Corporation. We also tested DPDK on LoongArch with some external applications, including: Pktgen-DPDK, OVS, VPP. The platform is currently marked as linux-only because there is no other OS than Linux support LoongArch host currently. The i40e PMD driver is disabled on LoongArch because of the absence of vector support in the current version. Similar to RISC-V, the compilation of following modules has been disabled by this commit and will be re-enabled in later commits as fixes are introduced: net/ixgbe, net/memif, net/tap, example/l3fwd. Signed-off-by: Min Zhou <zhoumin@loongson.cn> --- MAINTAINERS | 6 ++ app/test/test_xmmt_ops.h | 12 +++ .../loongarch/loongarch_loongarch64_linux_gcc | 16 ++++ config/loongarch/meson.build | 43 +++++++++ doc/guides/contributing/design.rst | 2 +- .../cross_build_dpdk_for_loongarch.rst | 87 +++++++++++++++++ doc/guides/linux_gsg/index.rst | 1 + doc/guides/nics/features.rst | 8 ++ doc/guides/nics/features/default.ini | 1 + doc/guides/rel_notes/release_22_11.rst | 7 ++ drivers/net/i40e/meson.build | 6 ++ drivers/net/ixgbe/meson.build | 6 ++ drivers/net/memif/meson.build | 6 ++ drivers/net/tap/meson.build | 6 ++ examples/l3fwd/meson.build | 6 ++ lib/eal/linux/eal_memory.c | 4 + lib/eal/loongarch/include/meson.build | 18 ++++ lib/eal/loongarch/include/rte_atomic.h | 47 ++++++++++ lib/eal/loongarch/include/rte_byteorder.h | 40 ++++++++ lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++ lib/eal/loongarch/include/rte_cycles.h | 47 ++++++++++ lib/eal/loongarch/include/rte_io.h | 18 ++++ lib/eal/loongarch/include/rte_memcpy.h | 61 ++++++++++++ lib/eal/loongarch/include/rte_pause.h | 24 +++++ .../loongarch/include/rte_power_intrinsics.h | 20 ++++ lib/eal/loongarch/include/rte_prefetch.h | 47 ++++++++++ lib/eal/loongarch/include/rte_rwlock.h | 42 +++++++++ lib/eal/loongarch/include/rte_spinlock.h | 64 +++++++++++++ lib/eal/loongarch/include/rte_vect.h | 65 +++++++++++++ lib/eal/loongarch/meson.build | 11 +++ lib/eal/loongarch/rte_cpuflags.c | 93 +++++++++++++++++++ lib/eal/loongarch/rte_cycles.c | 45 +++++++++ lib/eal/loongarch/rte_hypervisor.c | 11 +++ lib/eal/loongarch/rte_power_intrinsics.c | 53 +++++++++++ meson.build | 2 + 35 files changed, 963 insertions(+), 1 deletion(-) create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc create mode 100644 config/loongarch/meson.build create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst create mode 100644 lib/eal/loongarch/include/meson.build create mode 100644 lib/eal/loongarch/include/rte_atomic.h create mode 100644 lib/eal/loongarch/include/rte_byteorder.h create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h create mode 100644 lib/eal/loongarch/include/rte_cycles.h create mode 100644 lib/eal/loongarch/include/rte_io.h create mode 100644 lib/eal/loongarch/include/rte_memcpy.h create mode 100644 lib/eal/loongarch/include/rte_pause.h create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h create mode 100644 lib/eal/loongarch/include/rte_prefetch.h create mode 100644 lib/eal/loongarch/include/rte_rwlock.h create mode 100644 lib/eal/loongarch/include/rte_spinlock.h create mode 100644 lib/eal/loongarch/include/rte_vect.h create mode 100644 lib/eal/loongarch/meson.build create mode 100644 lib/eal/loongarch/rte_cpuflags.c create mode 100644 lib/eal/loongarch/rte_cycles.c create mode 100644 lib/eal/loongarch/rte_hypervisor.c create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c diff --git a/MAINTAINERS b/MAINTAINERS index 51d77460ec..6c5fcef749 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -294,6 +294,12 @@ F: app/*/*_neon.* F: examples/*/*_neon.* F: examples/common/neon/ +LoongArch +M: Min Zhou <zhoumin@loongson.cn> +F: config/loongarch/ +F: doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst +F: lib/eal/loongarch/ + IBM POWER (alpha) M: David Christensen <drc@linux.vnet.ibm.com> F: config/ppc/ diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h index 55f256599e..626aa9bcba 100644 --- a/app/test/test_xmmt_ops.h +++ b/app/test/test_xmmt_ops.h @@ -65,6 +65,18 @@ vect_set_epi32(int i3, int i2, int i1, int i0) return data; } +#elif defined(RTE_ARCH_LOONGARCH) + +#define vect_loadu_sil128(p) vect_load_128(p) + +/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */ +static __rte_always_inline xmm_t +vect_set_epi32(int i3, int i2, int i1, int i0) +{ + xmm_t data = (xmm_t){.u32 = {i0, i1, i2, i3}}; + + return data; +} #endif #endif /* _TEST_XMMT_OPS_H_ */ diff --git a/config/loongarch/loongarch_loongarch64_linux_gcc b/config/loongarch/loongarch_loongarch64_linux_gcc new file mode 100644 index 0000000000..0c44ae96e6 --- /dev/null +++ b/config/loongarch/loongarch_loongarch64_linux_gcc @@ -0,0 +1,16 @@ +[binaries] +c = 'loongarch64-unknown-linux-gnu-gcc' +cpp = 'loongarch64-unknown-linux-gnu-cpp' +ar = 'loongarch64-unknown-linux-gnu-gcc-ar' +strip = 'loongarch64-unknown-linux-gnu-strip' +pcap-config = '' + +[host_machine] +system = 'linux' +cpu_family = 'loongarch64' +cpu = '3a5000' +endian = 'little' + +[properties] +implementor_id = 'generic' +implementor_pn = 'default' diff --git a/config/loongarch/meson.build b/config/loongarch/meson.build new file mode 100644 index 0000000000..99dabef203 --- /dev/null +++ b/config/loongarch/meson.build @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2022 Loongson Technology Corporation Limited + +if not dpdk_conf.get('RTE_ARCH_64') + error('Only 64-bit compiles are supported for this platform type') +endif +dpdk_conf.set('RTE_ARCH', 'loongarch') +dpdk_conf.set('RTE_ARCH_LOONGARCH', 1) +dpdk_conf.set('RTE_FORCE_INTRINSICS', 1) + +machine_args_generic = [ + ['default', ['-march=loongarch64']], +] + +flags_generic = [ + ['RTE_MACHINE', '"loongarch64"'], + ['RTE_MAX_LCORE', 64], + ['RTE_MAX_NUMA_NODES', 16], + ['RTE_CACHE_LINE_SIZE', 64]] + +impl_generic = ['Generic loongarch', flags_generic, machine_args_generic] + +machine = [] +machine_args = [] + +machine = impl_generic +impl_pn = 'default' + +message('Implementer : ' + machine[0]) +foreach flag: machine[1] + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif +endforeach + +foreach marg: machine[2] + if marg[0] == impl_pn + foreach f: marg[1] + machine_args += f + endforeach + endif +endforeach +message(machine_args) diff --git a/doc/guides/contributing/design.rst b/doc/guides/contributing/design.rst index 0383afe5c8..d24a7ff6a0 100644 --- a/doc/guides/contributing/design.rst +++ b/doc/guides/contributing/design.rst @@ -42,7 +42,7 @@ Per Architecture Sources The following macro options can be used: * ``RTE_ARCH`` is a string that contains the name of the architecture. -* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures. +* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_LOONGARCH``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures. Per Execution Environment Sources ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst new file mode 100644 index 0000000000..3afc6d4933 --- /dev/null +++ b/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst @@ -0,0 +1,87 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2022 Loongson Technology Corporation Limited + +Cross compiling DPDK for LoongArch +================================== + +This chapter describes how to cross compile DPDK for LoongArch from x86 build +hosts. + +.. note:: + + Due to some of the code under review, the current Linux 5.19 cannot boot + on LoongArch system. There are still some Linux distributions that have + supported LoongArch host, such as Anolis OS, Kylin, Loongnix and UOS. These + distributions base on Linux kernel 4.19 supported by Loongson Corporation. + Because LoongArch is such a new platform with many fundamental pieces of + software still under development, it is currently recommended to cross + compile DPDK on x86 for LoongArch. + + +Prerequisites +------------- + +Ensure that you have all pre-requisites for building DPDK natively as those +will be required also for cross-compilation. + +Linux kernel +~~~~~~~~~~~~ + +Make sure that LoongArch host is running Linux kernel 4.19 or newer supported +by Loongson Corporation. The support for LoongArch in the current Linux 5.19 +is not complete because it still misses some patches to add for other +subsystems. + +GNU toolchain +------------- + +Obtain the cross toolchain +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The build process was tested using: + +* Latest `LoongArch GNU toolchain + <https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz>`_ + on Debian 10.4 or CentOS 8. + +Alternatively the toolchain may be built straight from the source via CLFS, to +do that follow the instructions on `CLFS for LoongArch64 +<https://github.com/sunhaiyong1978/CLFS-for-LoongArch>`_ github page. + +To download cross tools from github we can use the following command: + +.. code-block:: console + + wget -P /tmp/ https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz + +Unzip and add into the PATH +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +After downloading the cross-tools file, we need unzip and add those executable +binaries into the PATH as follows: + +.. code-block:: console + + tar -xvf /tmp/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz -C <cross_tool_install_dir> --strip-components 1 + export PATH=$PATH:<cross_tool_install_dir>/bin + + +Cross Compiling DPDK with GNU toolchain using Meson +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To cross-compile DPDK for generic LoongArch we can use the following command: + +.. code-block:: console + + meson cross-build --cross-file config/loongarch/loongarch_loongarch64_linux_gcc + ninja -C cross-build + +Supported cross-compilation targets +----------------------------------- + +Currently the following target is supported: + +* Generic LoongArch64 ISA: ``config/loongarch/loongarch_loongarch64_linux_gcc`` + +To add a new target support, a corresponding cross-file has to be added to +``config/loongarch`` directory. diff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst index 747552c385..c3e67bf9ec 100644 --- a/doc/guides/linux_gsg/index.rst +++ b/doc/guides/linux_gsg/index.rst @@ -14,6 +14,7 @@ Getting Started Guide for Linux sys_reqs build_dpdk cross_build_dpdk_for_arm64 + cross_build_dpdk_for_loongarch cross_build_dpdk_for_riscv linux_drivers build_sample_apps diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst index b4a8e9881c..2472049095 100644 --- a/doc/guides/nics/features.rst +++ b/doc/guides/nics/features.rst @@ -832,6 +832,14 @@ ARMv8 Support armv8a (64bit) architecture. +.. _nic_features_loongarch64: + +LoongArch64 +----------- + +Support 64-bit LoongArch architecture. + + .. _nic_features_power8: Power8 diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini index f7192cb0da..cbc17c0434 100644 --- a/doc/guides/nics/features/default.ini +++ b/doc/guides/nics/features/default.ini @@ -71,6 +71,7 @@ Linux = Windows = ARMv7 = ARMv8 = +LoongArch64 = Power8 = rv64 = x86-32 = diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst index 0b4740abd1..ac1f9a924c 100644 --- a/doc/guides/rel_notes/release_22_11.rst +++ b/doc/guides/rel_notes/release_22_11.rst @@ -96,6 +96,13 @@ New Features * Added ``rte_event_eth_tx_adapter_queue_stop`` to stop the Tx Adapter from enqueueing any packets to the Tx queue. +* **Added initial LoongArch architecture support.** + + * Added EAL implementation for LoongArch architecture. The initial devices + the porting was tested on included Loongson 3A5000, Loongson 3C5000 and + Loongson 3C5000L. In theory this implementation should work with any target + based on ``LoongArch`` ISA. + Removed Items ------------- diff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build index 84fd42754e..16fd491b9a 100644 --- a/drivers/net/i40e/meson.build +++ b/drivers/net/i40e/meson.build @@ -7,6 +7,12 @@ if arch_subdir == 'riscv' subdir_done() endif +if arch_subdir == 'loongarch' + build = false + reason = 'not supported on LoongArch' + subdir_done() +endif + cflags += ['-DPF_DRIVER', '-DVF_DRIVER', '-DINTEGRATED_VF', diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build index a18908ef7c..80ab012448 100644 --- a/drivers/net/ixgbe/meson.build +++ b/drivers/net/ixgbe/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation +if arch_subdir == 'loongarch' + build = false + reason = 'not supported on LoongArch' + subdir_done() +endif + cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS'] subdir('base') diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build index 680bc8631c..30c0fbc798 100644 --- a/drivers/net/memif/meson.build +++ b/drivers/net/memif/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright 2018-2019 Cisco Systems, Inc. All rights reserved. +if arch_subdir == 'loongarch' + build = false + reason = 'not supported on LoongArch' + subdir_done() +endif + if not is_linux build = false reason = 'only supported on Linux' diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build index c09713a67b..f0d03069cd 100644 --- a/drivers/net/tap/meson.build +++ b/drivers/net/tap/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright 2018 Luca Boccassi <bluca@debian.org> +if arch_subdir == 'loongarch' + build = false + reason = 'not supported on LoongArch' + subdir_done() +endif + if not is_linux build = false reason = 'only supported on Linux' diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build index b40244a941..d2f2d96099 100644 --- a/examples/l3fwd/meson.build +++ b/examples/l3fwd/meson.build @@ -6,6 +6,12 @@ # To build this example as a standalone application with an already-installed # DPDK instance, use 'make' +if arch_subdir == 'loongarch' + build = false + reason = 'not supported on LoongArch' + subdir_done() +endif + allow_experimental_apis = true deps += ['acl', 'hash', 'lpm', 'fib', 'eventdev'] sources = files( diff --git a/lib/eal/linux/eal_memory.c b/lib/eal/linux/eal_memory.c index c890c42106..60fc8cc6ca 100644 --- a/lib/eal/linux/eal_memory.c +++ b/lib/eal/linux/eal_memory.c @@ -77,7 +77,11 @@ uint64_t eal_get_baseaddr(void) * rte_mem_check_dma_mask for ensuring all memory is within supported * range. */ +#if defined(RTE_ARCH_LOONGARCH) + return 0x7000000000ULL; +#else return 0x100000000ULL; +#endif } /* diff --git a/lib/eal/loongarch/include/meson.build b/lib/eal/loongarch/include/meson.build new file mode 100644 index 0000000000..6e8d12601a --- /dev/null +++ b/lib/eal/loongarch/include/meson.build @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2022 Loongson Technology Corporation Limited + +arch_headers = files( + 'rte_atomic.h', + 'rte_byteorder.h', + 'rte_cpuflags.h', + 'rte_cycles.h', + 'rte_io.h', + 'rte_memcpy.h', + 'rte_pause.h', + 'rte_power_intrinsics.h', + 'rte_prefetch.h', + 'rte_rwlock.h', + 'rte_spinlock.h', + 'rte_vect.h', +) +install_headers(arch_headers, subdir: get_option('include_subdir_arch')) diff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h new file mode 100644 index 0000000000..b0ddcab72e --- /dev/null +++ b/lib/eal/loongarch/include/rte_atomic.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_ATOMIC_LOONGARCH_H_ +#define _RTE_ATOMIC_LOONGARCH_H_ + +#ifndef RTE_FORCE_INTRINSICS +# error Platform must be built with RTE_FORCE_INTRINSICS +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rte_common.h> +#include "generic/rte_atomic.h" + +#define rte_mb() do { asm volatile("dbar 0":::"memory"); } while (0) + +#define rte_wmb() rte_mb() + +#define rte_rmb() rte_mb() + +#define rte_smp_mb() rte_mb() + +#define rte_smp_wmb() rte_mb() + +#define rte_smp_rmb() rte_mb() + +#define rte_io_mb() rte_mb() + +#define rte_io_wmb() rte_mb() + +#define rte_io_rmb() rte_mb() + +static __rte_always_inline void +rte_atomic_thread_fence(int memorder) +{ + __atomic_thread_fence(memorder); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_ATOMIC_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_byteorder.h b/lib/eal/loongarch/include/rte_byteorder.h new file mode 100644 index 0000000000..ba27998497 --- /dev/null +++ b/lib/eal/loongarch/include/rte_byteorder.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_BYTEORDER_LOONGARCH_H_ +#define _RTE_BYTEORDER_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_byteorder.h" + +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + +#define rte_cpu_to_le_16(x) (x) +#define rte_cpu_to_le_32(x) (x) +#define rte_cpu_to_le_64(x) (x) + +#define rte_cpu_to_be_16(x) rte_bswap16(x) +#define rte_cpu_to_be_32(x) rte_bswap32(x) +#define rte_cpu_to_be_64(x) rte_bswap64(x) + +#define rte_le_to_cpu_16(x) (x) +#define rte_le_to_cpu_32(x) (x) +#define rte_le_to_cpu_64(x) (x) + +#define rte_be_to_cpu_16(x) rte_bswap16(x) +#define rte_be_to_cpu_32(x) rte_bswap32(x) +#define rte_be_to_cpu_64(x) rte_bswap64(x) + +#else /* RTE_BIG_ENDIAN */ +#error "LoongArch not support big endian!" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_BYTEORDER_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_cpuflags.h b/lib/eal/loongarch/include/rte_cpuflags.h new file mode 100644 index 0000000000..d9121a00a8 --- /dev/null +++ b/lib/eal/loongarch/include/rte_cpuflags.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_CPUFLAGS_LOONGARCH_H_ +#define _RTE_CPUFLAGS_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Enumeration of all CPU features supported + */ +enum rte_cpu_flag_t { + RTE_CPUFLAG_CPUCFG = 0, + RTE_CPUFLAG_LAM, + RTE_CPUFLAG_UAL, + RTE_CPUFLAG_FPU, + RTE_CPUFLAG_LSX, + RTE_CPUFLAG_LASX, + RTE_CPUFLAG_CRC32, + RTE_CPUFLAG_COMPLEX, + RTE_CPUFLAG_CRYPTO, + RTE_CPUFLAG_LVZ, + RTE_CPUFLAG_LBT_X86, + RTE_CPUFLAG_LBT_ARM, + RTE_CPUFLAG_LBT_MIPS, + /* The last item */ + RTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */ +}; + +#include "generic/rte_cpuflags.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_CPUFLAGS_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_cycles.h b/lib/eal/loongarch/include/rte_cycles.h new file mode 100644 index 0000000000..0f1539be1b --- /dev/null +++ b/lib/eal/loongarch/include/rte_cycles.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_CYCLES_LOONGARCH_H_ +#define _RTE_CYCLES_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_cycles.h" + +/** + * Read the time base register. + * + * @return + * The time base for this lcore. + */ +static inline uint64_t +rte_rdtsc(void) +{ + uint64_t count; + + __asm__ __volatile__ ( + "rdtime.d %[cycles], $zero\n" + : [cycles] "=r" (count) + :: + ); + return count; +} + +static inline uint64_t +rte_rdtsc_precise(void) +{ + rte_mb(); + return rte_rdtsc(); +} + +static inline uint64_t +rte_get_tsc_cycles(void) { return rte_rdtsc(); } + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_CYCLES_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_io.h b/lib/eal/loongarch/include/rte_io.h new file mode 100644 index 0000000000..af152a727a --- /dev/null +++ b/lib/eal/loongarch/include/rte_io.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_IO_LOONGARCH_H_ +#define _RTE_IO_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_io.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_IO_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_memcpy.h b/lib/eal/loongarch/include/rte_memcpy.h new file mode 100644 index 0000000000..e7b91e9ce4 --- /dev/null +++ b/lib/eal/loongarch/include/rte_memcpy.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_MEMCPY_LOONGARCH_H_ +#define _RTE_MEMCPY_LOONGARCH_H_ + +#include <stdint.h> +#include <string.h> + +#include "rte_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_memcpy.h" + +static inline void +rte_mov16(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 16); +} + +static inline void +rte_mov32(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 32); +} + +static inline void +rte_mov48(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 48); +} + +static inline void +rte_mov64(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 64); +} + +static inline void +rte_mov128(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 128); +} + +static inline void +rte_mov256(uint8_t *dst, const uint8_t *src) +{ + memcpy(dst, src, 256); +} + +#define rte_memcpy(d, s, n) memcpy((d), (s), (n)) + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_MEMCPY_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_pause.h b/lib/eal/loongarch/include/rte_pause.h new file mode 100644 index 0000000000..438de23128 --- /dev/null +++ b/lib/eal/loongarch/include/rte_pause.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_PAUSE_LOONGARCH_H_ +#define _RTE_PAUSE_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rte_atomic.h" + +#include "generic/rte_pause.h" + +static inline void rte_pause(void) +{ +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_PAUSE_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_power_intrinsics.h b/lib/eal/loongarch/include/rte_power_intrinsics.h new file mode 100644 index 0000000000..b6a2c0d82e --- /dev/null +++ b/lib/eal/loongarch/include/rte_power_intrinsics.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_POWER_INTRINSIC_LOONGARCH_H_ +#define _RTE_POWER_INTRINSIC_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rte_common.h> + +#include "generic/rte_power_intrinsics.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_POWER_INTRINSIC_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_prefetch.h b/lib/eal/loongarch/include/rte_prefetch.h new file mode 100644 index 0000000000..0fd9262ea8 --- /dev/null +++ b/lib/eal/loongarch/include/rte_prefetch.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_PREFETCH_LOONGARCH_H_ +#define _RTE_PREFETCH_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rte_common.h> +#include "generic/rte_prefetch.h" + +static inline void rte_prefetch0(const volatile void *p) +{ + __builtin_prefetch((const void *)(uintptr_t)p, 0, 3); +} + +static inline void rte_prefetch1(const volatile void *p) +{ + __builtin_prefetch((const void *)(uintptr_t)p, 0, 2); +} + +static inline void rte_prefetch2(const volatile void *p) +{ + __builtin_prefetch((const void *)(uintptr_t)p, 0, 1); +} + +static inline void rte_prefetch_non_temporal(const volatile void *p) +{ + /* non-temporal version not available, fallback to rte_prefetch0 */ + rte_prefetch0(p); +} + +__rte_experimental +static inline void +rte_cldemote(const volatile void *p) +{ + RTE_SET_USED(p); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_PREFETCH_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_rwlock.h b/lib/eal/loongarch/include/rte_rwlock.h new file mode 100644 index 0000000000..aac6f60120 --- /dev/null +++ b/lib/eal/loongarch/include/rte_rwlock.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_RWLOCK_LOONGARCH_H_ +#define _RTE_RWLOCK_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_rwlock.h" + +static inline void +rte_rwlock_read_lock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_read_lock(rwl); +} + +static inline void +rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_read_unlock(rwl); +} + +static inline void +rte_rwlock_write_lock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_write_lock(rwl); +} + +static inline void +rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl) +{ + rte_rwlock_write_unlock(rwl); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_RWLOCK_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_spinlock.h b/lib/eal/loongarch/include/rte_spinlock.h new file mode 100644 index 0000000000..dd07538c7f --- /dev/null +++ b/lib/eal/loongarch/include/rte_spinlock.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_SPINLOCK_LOONGARCH_H_ +#define _RTE_SPINLOCK_LOONGARCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rte_common.h> +#include "generic/rte_spinlock.h" + +#ifndef RTE_FORCE_INTRINSICS +# error Platform must be built with RTE_FORCE_INTRINSICS +#endif + +static inline int rte_tm_supported(void) +{ + return 0; +} + +static inline void +rte_spinlock_lock_tm(rte_spinlock_t *sl) +{ + rte_spinlock_lock(sl); /* fall-back */ +} + +static inline int +rte_spinlock_trylock_tm(rte_spinlock_t *sl) +{ + return rte_spinlock_trylock(sl); +} + +static inline void +rte_spinlock_unlock_tm(rte_spinlock_t *sl) +{ + rte_spinlock_unlock(sl); +} + +static inline void +rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr) +{ + rte_spinlock_recursive_lock(slr); /* fall-back */ +} + +static inline void +rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr) +{ + rte_spinlock_recursive_unlock(slr); +} + +static inline int +rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr) +{ + return rte_spinlock_recursive_trylock(slr); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_SPINLOCK_LOONGARCH_H_ */ diff --git a/lib/eal/loongarch/include/rte_vect.h b/lib/eal/loongarch/include/rte_vect.h new file mode 100644 index 0000000000..5951a2674c --- /dev/null +++ b/lib/eal/loongarch/include/rte_vect.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#ifndef _RTE_VECT_LOONGARCH_H_ +#define _RTE_VECT_LOONGARCH_H_ + +#include <stdint.h> +#include "generic/rte_vect.h" +#include "rte_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED + +typedef union xmm { + int8_t i8[16]; + int16_t i16[8]; + int32_t i32[4]; + int64_t i64[2]; + uint8_t u8[16]; + uint16_t u16[8]; + uint32_t u32[4]; + uint64_t u64[2]; + double pd[2]; +} __rte_aligned(16) xmm_t; + +#define XMM_SIZE (sizeof(xmm_t)) +#define XMM_MASK (XMM_SIZE - 1) + +typedef union rte_xmm { + xmm_t x; + uint8_t u8[XMM_SIZE / sizeof(uint8_t)]; + uint16_t u16[XMM_SIZE / sizeof(uint16_t)]; + uint32_t u32[XMM_SIZE / sizeof(uint32_t)]; + uint64_t u64[XMM_SIZE / sizeof(uint64_t)]; + double pd[XMM_SIZE / sizeof(double)]; +} __rte_aligned(16) rte_xmm_t; + +static inline xmm_t +vect_load_128(void *p) +{ + xmm_t ret = *((xmm_t *)p); + + return ret; +} + +static inline xmm_t +vect_and(xmm_t data, xmm_t mask) +{ + rte_xmm_t ret = {.x = data }; + rte_xmm_t m = {.x = mask }; + ret.u64[0] &= m.u64[0]; + ret.u64[1] &= m.u64[1]; + + return ret.x; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/eal/loongarch/meson.build b/lib/eal/loongarch/meson.build new file mode 100644 index 0000000000..4dcc27babb --- /dev/null +++ b/lib/eal/loongarch/meson.build @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2022 Loongson Technology Corporation Limited + +subdir('include') + +sources += files( + 'rte_cpuflags.c', + 'rte_cycles.c', + 'rte_hypervisor.c', + 'rte_power_intrinsics.c', +) diff --git a/lib/eal/loongarch/rte_cpuflags.c b/lib/eal/loongarch/rte_cpuflags.c new file mode 100644 index 0000000000..0a75ca58d4 --- /dev/null +++ b/lib/eal/loongarch/rte_cpuflags.c @@ -0,0 +1,93 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include "rte_cpuflags.h" + +#include <elf.h> +#include <fcntl.h> +#include <assert.h> +#include <unistd.h> +#include <string.h> + +/* Symbolic values for the entries in the auxiliary table */ +#define AT_HWCAP 16 + +/* software based registers */ +enum cpu_register_t { + REG_NONE = 0, + REG_HWCAP, + REG_MAX +}; + +typedef uint32_t hwcap_registers_t[REG_MAX]; + +struct feature_entry { + uint32_t reg; + uint32_t bit; +#define CPU_FLAG_NAME_MAX_LEN 64 + char name[CPU_FLAG_NAME_MAX_LEN]; +}; + +#define FEAT_DEF(name, reg, bit) \ + [RTE_CPUFLAG_##name] = {reg, bit, #name}, + +const struct feature_entry rte_cpu_feature_table[] = { + FEAT_DEF(CPUCFG, REG_HWCAP, 0) + FEAT_DEF(LAM, REG_HWCAP, 1) + FEAT_DEF(UAL, REG_HWCAP, 2) + FEAT_DEF(FPU, REG_HWCAP, 3) + FEAT_DEF(LSX, REG_HWCAP, 4) + FEAT_DEF(LASX, REG_HWCAP, 5) + FEAT_DEF(CRC32, REG_HWCAP, 6) + FEAT_DEF(COMPLEX, REG_HWCAP, 7) + FEAT_DEF(CRYPTO, REG_HWCAP, 8) + FEAT_DEF(LVZ, REG_HWCAP, 9) + FEAT_DEF(LBT_X86, REG_HWCAP, 10) + FEAT_DEF(LBT_ARM, REG_HWCAP, 11) + FEAT_DEF(LBT_MIPS, REG_HWCAP, 12) +}; + +/* + * Read AUXV software register and get cpu features for LoongArch + */ +static void +rte_cpu_get_features(hwcap_registers_t out) +{ + out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); +} + +/* + * Checks if a particular flag is available on current machine. + */ +int +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) +{ + const struct feature_entry *feat; + hwcap_registers_t regs = {0}; + + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return -ENOENT; + + feat = &rte_cpu_feature_table[feature]; + if (feat->reg == REG_NONE) + return -EFAULT; + + rte_cpu_get_features(regs); + return (regs[feat->reg] >> feat->bit) & 1; +} + +const char * +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) +{ + if (feature >= RTE_CPUFLAG_NUMFLAGS) + return NULL; + return rte_cpu_feature_table[feature].name; +} + +void +rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics) +{ + memset(intrinsics, 0, sizeof(*intrinsics)); +} diff --git a/lib/eal/loongarch/rte_cycles.c b/lib/eal/loongarch/rte_cycles.c new file mode 100644 index 0000000000..582601d335 --- /dev/null +++ b/lib/eal/loongarch/rte_cycles.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include "eal_private.h" + +#define LOONGARCH_CPUCFG4 0x4 +#define CPUCFG4_CCFREQ_MASK 0xFFFFFFFF +#define CPUCFG4_CCFREQ_SHIFT 0 + +#define LOONGARCH_CPUCFG5 0x5 +#define CPUCFG5_CCMUL_MASK 0xFFFF +#define CPUCFG5_CCMUL_SHIFT 0 + +#define CPUCFG5_CCDIV_MASK 0xFFFF0000 +#define CPUCFG5_CCDIV_SHIFT 16 + +static __rte_noinline uint32_t +read_cpucfg(int arg) +{ + int ret = 0; + + __asm__ __volatile__ ( + "cpucfg %[var], %[index]\n" + : [var]"=r"(ret) + : [index]"r"(arg) + : + ); + + return ret; +} + +uint64_t +get_tsc_freq_arch(void) +{ + uint32_t base_freq, mul_factor, div_factor; + + base_freq = read_cpucfg(LOONGARCH_CPUCFG4); + mul_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCMUL_MASK) >> + CPUCFG5_CCMUL_SHIFT; + div_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCDIV_MASK) >> + CPUCFG5_CCDIV_SHIFT; + + return base_freq * mul_factor / div_factor; +} diff --git a/lib/eal/loongarch/rte_hypervisor.c b/lib/eal/loongarch/rte_hypervisor.c new file mode 100644 index 0000000000..d044906f71 --- /dev/null +++ b/lib/eal/loongarch/rte_hypervisor.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include "rte_hypervisor.h" + +enum rte_hypervisor +rte_hypervisor_get(void) +{ + return RTE_HYPERVISOR_UNKNOWN; +} diff --git a/lib/eal/loongarch/rte_power_intrinsics.c b/lib/eal/loongarch/rte_power_intrinsics.c new file mode 100644 index 0000000000..a8969c260e --- /dev/null +++ b/lib/eal/loongarch/rte_power_intrinsics.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Loongson Technology Corporation Limited + */ + +#include <errno.h> + +#include "rte_power_intrinsics.h" + +/** + * This function is not supported on LOONGARCH. + */ +int +rte_power_monitor(const struct rte_power_monitor_cond *pmc, + const uint64_t tsc_timestamp) +{ + RTE_SET_USED(pmc); + RTE_SET_USED(tsc_timestamp); + + return -ENOTSUP; +} + +/** + * This function is not supported on LOONGARCH. + */ +int +rte_power_pause(const uint64_t tsc_timestamp) +{ + RTE_SET_USED(tsc_timestamp); + + return -ENOTSUP; +} + +/** + * This function is not supported on LOONGARCH. + */ +int +rte_power_monitor_wakeup(const unsigned int lcore_id) +{ + RTE_SET_USED(lcore_id); + + return -ENOTSUP; +} + +int +rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[], + const uint32_t num, const uint64_t tsc_timestamp) +{ + RTE_SET_USED(pmc); + RTE_SET_USED(num); + RTE_SET_USED(tsc_timestamp); + + return -ENOTSUP; +} diff --git a/meson.build b/meson.build index 7d6643da3a..de718974d4 100644 --- a/meson.build +++ b/meson.build @@ -56,6 +56,8 @@ elif host_machine.cpu_family().startswith('ppc') arch_subdir = 'ppc' elif host_machine.cpu_family().startswith('riscv') arch_subdir = 'riscv' +elif host_machine.cpu_family().startswith('loongarch') + arch_subdir = 'loongarch' endif # configure the build, and make sure configs here and in config folder are -- 2.31.1 ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v7 1/7] eal/loongarch: support LoongArch architecture 2022-09-30 8:02 ` [PATCH v7 1/7] eal/loongarch: support " Min Zhou @ 2022-10-03 17:15 ` David Marchand 2022-10-04 8:49 ` zhoumin 0 siblings, 1 reply; 20+ messages in thread From: David Marchand @ 2022-10-03 17:15 UTC (permalink / raw) To: Min Zhou Cc: thomas, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo On Fri, Sep 30, 2022 at 10:02 AM Min Zhou <zhoumin@loongson.cn> wrote: > > Add all necessary elements for DPDK to compile and run EAL on > LoongArch64 Soc. > > This includes: > > - EAL library implementation for LoongArch ISA. > - meson build structure for 'loongarch' architecture. > RTE_ARCH_LOONGARCH define is added for architecture identification. > - xmm_t structure operation stubs as there is no vector support in > the current version for LoongArch. > > Compilation was tested on Debian and CentOS using loongarch64 > cross-compile toolchain from x86 build hosts. Functions were tested > on Loongnix and Kylin which are two Linux distributions supported > LoongArch host based on Linux 4.19 maintained by Loongson > Corporation. > > We also tested DPDK on LoongArch with some external applications, > including: Pktgen-DPDK, OVS, VPP. > > The platform is currently marked as linux-only because there is no > other OS than Linux support LoongArch host currently. > > The i40e PMD driver is disabled on LoongArch because of the absence > of vector support in the current version. > > Similar to RISC-V, the compilation of following modules has been > disabled by this commit and will be re-enabled in later commits as > fixes are introduced: > net/ixgbe, net/memif, net/tap, example/l3fwd. > > Signed-off-by: Min Zhou <zhoumin@loongson.cn> > --- > MAINTAINERS | 6 ++ > app/test/test_xmmt_ops.h | 12 +++ > .../loongarch/loongarch_loongarch64_linux_gcc | 16 ++++ > config/loongarch/meson.build | 43 +++++++++ Please update devtools/test-meson-builds.sh in this patch. I tested the compilation of the series per patch (I caught one issue in net/bnxt which I posted a fix for), with this diff: @@ -260,6 +260,10 @@ build build-x86-mingw $f skipABI -Dexamples=helloworld f=$srcdir/config/arm/arm64_armv8_linux_gcc build build-arm64-generic-gcc $f ABI $use_shared +# generic LoongArch +f=$srcdir/config/loongarch/loongarch_loongarch64_linux_gcc +build build-loongarch64-generic-gcc $f ABI $use_shared + # IBM POWER f=$srcdir/config/ppc/ppc64le-power8-linux-gcc build build-ppc64-power8-gcc $f ABI $use_shared > doc/guides/contributing/design.rst | 2 +- > .../cross_build_dpdk_for_loongarch.rst | 87 +++++++++++++++++ > doc/guides/linux_gsg/index.rst | 1 + > doc/guides/nics/features.rst | 8 ++ > doc/guides/nics/features/default.ini | 1 + > doc/guides/rel_notes/release_22_11.rst | 7 ++ > drivers/net/i40e/meson.build | 6 ++ > drivers/net/ixgbe/meson.build | 6 ++ > drivers/net/memif/meson.build | 6 ++ > drivers/net/tap/meson.build | 6 ++ > examples/l3fwd/meson.build | 6 ++ > lib/eal/linux/eal_memory.c | 4 + > lib/eal/loongarch/include/meson.build | 18 ++++ > lib/eal/loongarch/include/rte_atomic.h | 47 ++++++++++ > lib/eal/loongarch/include/rte_byteorder.h | 40 ++++++++ > lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++ > lib/eal/loongarch/include/rte_cycles.h | 47 ++++++++++ > lib/eal/loongarch/include/rte_io.h | 18 ++++ > lib/eal/loongarch/include/rte_memcpy.h | 61 ++++++++++++ > lib/eal/loongarch/include/rte_pause.h | 24 +++++ > .../loongarch/include/rte_power_intrinsics.h | 20 ++++ > lib/eal/loongarch/include/rte_prefetch.h | 47 ++++++++++ > lib/eal/loongarch/include/rte_rwlock.h | 42 +++++++++ > lib/eal/loongarch/include/rte_spinlock.h | 64 +++++++++++++ > lib/eal/loongarch/include/rte_vect.h | 65 +++++++++++++ > lib/eal/loongarch/meson.build | 11 +++ > lib/eal/loongarch/rte_cpuflags.c | 93 +++++++++++++++++++ > lib/eal/loongarch/rte_cycles.c | 45 +++++++++ > lib/eal/loongarch/rte_hypervisor.c | 11 +++ > lib/eal/loongarch/rte_power_intrinsics.c | 53 +++++++++++ > meson.build | 2 + > 35 files changed, 963 insertions(+), 1 deletion(-) > create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc > create mode 100644 config/loongarch/meson.build > create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst > create mode 100644 lib/eal/loongarch/include/meson.build > create mode 100644 lib/eal/loongarch/include/rte_atomic.h > create mode 100644 lib/eal/loongarch/include/rte_byteorder.h > create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h > create mode 100644 lib/eal/loongarch/include/rte_cycles.h > create mode 100644 lib/eal/loongarch/include/rte_io.h > create mode 100644 lib/eal/loongarch/include/rte_memcpy.h > create mode 100644 lib/eal/loongarch/include/rte_pause.h > create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h > create mode 100644 lib/eal/loongarch/include/rte_prefetch.h > create mode 100644 lib/eal/loongarch/include/rte_rwlock.h > create mode 100644 lib/eal/loongarch/include/rte_spinlock.h > create mode 100644 lib/eal/loongarch/include/rte_vect.h > create mode 100644 lib/eal/loongarch/meson.build > create mode 100644 lib/eal/loongarch/rte_cpuflags.c > create mode 100644 lib/eal/loongarch/rte_cycles.c > create mode 100644 lib/eal/loongarch/rte_hypervisor.c > create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 51d77460ec..6c5fcef749 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -294,6 +294,12 @@ F: app/*/*_neon.* > F: examples/*/*_neon.* > F: examples/common/neon/ > > +LoongArch > +M: Min Zhou <zhoumin@loongson.cn> > +F: config/loongarch/ > +F: doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst > +F: lib/eal/loongarch/ > + > IBM POWER (alpha) > M: David Christensen <drc@linux.vnet.ibm.com> > F: config/ppc/ > diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h > index 55f256599e..626aa9bcba 100644 > --- a/app/test/test_xmmt_ops.h > +++ b/app/test/test_xmmt_ops.h > @@ -65,6 +65,18 @@ vect_set_epi32(int i3, int i2, int i1, int i0) > return data; > } > > +#elif defined(RTE_ARCH_LOONGARCH) > + > +#define vect_loadu_sil128(p) vect_load_128(p) > + > +/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */ > +static __rte_always_inline xmm_t > +vect_set_epi32(int i3, int i2, int i1, int i0) > +{ > + xmm_t data = (xmm_t){.u32 = {i0, i1, i2, i3}}; > + > + return data; > +} > #endif > > #endif /* _TEST_XMMT_OPS_H_ */ > diff --git a/config/loongarch/loongarch_loongarch64_linux_gcc b/config/loongarch/loongarch_loongarch64_linux_gcc > new file mode 100644 > index 0000000000..0c44ae96e6 > --- /dev/null > +++ b/config/loongarch/loongarch_loongarch64_linux_gcc > @@ -0,0 +1,16 @@ > +[binaries] > +c = 'loongarch64-unknown-linux-gnu-gcc' > +cpp = 'loongarch64-unknown-linux-gnu-cpp' > +ar = 'loongarch64-unknown-linux-gnu-gcc-ar' > +strip = 'loongarch64-unknown-linux-gnu-strip' > +pcap-config = '' > + > +[host_machine] > +system = 'linux' > +cpu_family = 'loongarch64' > +cpu = '3a5000' > +endian = 'little' > + > +[properties] > +implementor_id = 'generic' > +implementor_pn = 'default' Two things to fix here: - Please add ccache, see e3fd286ec471 ("build: add ccache for cross compilation") - the cpp meson variable should refer to a c++ compiler. See f75dd6d3b121 ("config: fix C++ cross compiler for Arm and PPC") > diff --git a/config/loongarch/meson.build b/config/loongarch/meson.build > new file mode 100644 > index 0000000000..99dabef203 > --- /dev/null > +++ b/config/loongarch/meson.build > @@ -0,0 +1,43 @@ > +# SPDX-License-Identifier: BSD-3-Clause > +# Copyright(c) 2022 Loongson Technology Corporation Limited > + > +if not dpdk_conf.get('RTE_ARCH_64') > + error('Only 64-bit compiles are supported for this platform type') > +endif > +dpdk_conf.set('RTE_ARCH', 'loongarch') > +dpdk_conf.set('RTE_ARCH_LOONGARCH', 1) > +dpdk_conf.set('RTE_FORCE_INTRINSICS', 1) > + > +machine_args_generic = [ > + ['default', ['-march=loongarch64']], > +] > + > +flags_generic = [ > + ['RTE_MACHINE', '"loongarch64"'], > + ['RTE_MAX_LCORE', 64], > + ['RTE_MAX_NUMA_NODES', 16], > + ['RTE_CACHE_LINE_SIZE', 64]] > + > +impl_generic = ['Generic loongarch', flags_generic, machine_args_generic] > + > +machine = [] > +machine_args = [] > + > +machine = impl_generic > +impl_pn = 'default' > + > +message('Implementer : ' + machine[0]) > +foreach flag: machine[1] > + if flag.length() > 0 > + dpdk_conf.set(flag[0], flag[1]) > + endif > +endforeach > + > +foreach marg: machine[2] > + if marg[0] == impl_pn > + foreach f: marg[1] > + machine_args += f > + endforeach > + endif > +endforeach > +message(machine_args) cpu_instruction_set is not supported, though I am not sure LoongArch needs it. Maybe something to add in the future but not blocking atm. > diff --git a/doc/guides/contributing/design.rst b/doc/guides/contributing/design.rst > index 0383afe5c8..d24a7ff6a0 100644 > --- a/doc/guides/contributing/design.rst > +++ b/doc/guides/contributing/design.rst > @@ -42,7 +42,7 @@ Per Architecture Sources > The following macro options can be used: > > * ``RTE_ARCH`` is a string that contains the name of the architecture. > -* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures. > +* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_LOONGARCH``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures. > > Per Execution Environment Sources > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst > new file mode 100644 > index 0000000000..3afc6d4933 > --- /dev/null > +++ b/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst > @@ -0,0 +1,87 @@ > +.. SPDX-License-Identifier: BSD-3-Clause > + Copyright(c) 2022 Loongson Technology Corporation Limited > + > +Cross compiling DPDK for LoongArch > +================================== > + > +This chapter describes how to cross compile DPDK for LoongArch from x86 build > +hosts. > + > +.. note:: > + > + Due to some of the code under review, the current Linux 5.19 cannot boot > + on LoongArch system. There are still some Linux distributions that have > + supported LoongArch host, such as Anolis OS, Kylin, Loongnix and UOS. These > + distributions base on Linux kernel 4.19 supported by Loongson Corporation. > + Because LoongArch is such a new platform with many fundamental pieces of > + software still under development, it is currently recommended to cross > + compile DPDK on x86 for LoongArch. > + > + > +Prerequisites > +------------- > + > +Ensure that you have all pre-requisites for building DPDK natively as those > +will be required also for cross-compilation. > + > +Linux kernel > +~~~~~~~~~~~~ > + > +Make sure that LoongArch host is running Linux kernel 4.19 or newer supported > +by Loongson Corporation. The support for LoongArch in the current Linux 5.19 > +is not complete because it still misses some patches to add for other > +subsystems. > + > +GNU toolchain > +------------- > + > +Obtain the cross toolchain > +~~~~~~~~~~~~~~~~~~~~~~~~~~ > + > +The build process was tested using: > + > +* Latest `LoongArch GNU toolchain > + <https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz>`_ > + on Debian 10.4 or CentOS 8. > + > +Alternatively the toolchain may be built straight from the source via CLFS, to > +do that follow the instructions on `CLFS for LoongArch64 > +<https://github.com/sunhaiyong1978/CLFS-for-LoongArch>`_ github page. > + > +To download cross tools from github we can use the following command: > + > +.. code-block:: console > + > + wget -P /tmp/ https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz > + Some people (like me ;-)) will want to generate their own cross toolchain. I tried your script, and I added some comments in the thread where you provided it. I think adding the whole script in the documentation is too much. I would lean to adding a link to this thread in the documentation instead. https://inbox.dpdk.org/dev/53b50799-cb29-7ee6-be89-4fe21566e127@loongson.cn/T/#m1da99578f85894a4ddcd8e39d8239869e6a501d1 Opinion? > +Unzip and add into the PATH > +~~~~~~~~~~~~~~~~~~~~~~~~~~~ > + > +After downloading the cross-tools file, we need unzip and add those executable > +binaries into the PATH as follows: > + > +.. code-block:: console > + > + tar -xvf /tmp/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz -C <cross_tool_install_dir> --strip-components 1 > + export PATH=$PATH:<cross_tool_install_dir>/bin > + > + > +Cross Compiling DPDK with GNU toolchain using Meson > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > + > +To cross-compile DPDK for generic LoongArch we can use the following command: > + > +.. code-block:: console > + > + meson cross-build --cross-file config/loongarch/loongarch_loongarch64_linux_gcc > + ninja -C cross-build > + > +Supported cross-compilation targets > +----------------------------------- > + > +Currently the following target is supported: > + > +* Generic LoongArch64 ISA: ``config/loongarch/loongarch_loongarch64_linux_gcc`` > + > +To add a new target support, a corresponding cross-file has to be added to > +``config/loongarch`` directory. > diff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst > index 747552c385..c3e67bf9ec 100644 > --- a/doc/guides/linux_gsg/index.rst > +++ b/doc/guides/linux_gsg/index.rst > @@ -14,6 +14,7 @@ Getting Started Guide for Linux > sys_reqs > build_dpdk > cross_build_dpdk_for_arm64 > + cross_build_dpdk_for_loongarch > cross_build_dpdk_for_riscv > linux_drivers > build_sample_apps > diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst > index b4a8e9881c..2472049095 100644 > --- a/doc/guides/nics/features.rst > +++ b/doc/guides/nics/features.rst > @@ -832,6 +832,14 @@ ARMv8 > Support armv8a (64bit) architecture. > > > +.. _nic_features_loongarch64: Hum, one comment. This is not related to your patch, so you can keep as you posted. Those anchors are unused, we should remove them all. > + > +LoongArch64 > +----------- > + > +Support 64-bit LoongArch architecture. > + > + > .. _nic_features_power8: > > Power8 > diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini > index f7192cb0da..cbc17c0434 100644 > --- a/doc/guides/nics/features/default.ini > +++ b/doc/guides/nics/features/default.ini > @@ -71,6 +71,7 @@ Linux = > Windows = > ARMv7 = > ARMv8 = > +LoongArch64 = > Power8 = > rv64 = > x86-32 = > diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst > index 0b4740abd1..ac1f9a924c 100644 > --- a/doc/guides/rel_notes/release_22_11.rst > +++ b/doc/guides/rel_notes/release_22_11.rst > @@ -96,6 +96,13 @@ New Features > * Added ``rte_event_eth_tx_adapter_queue_stop`` to stop the Tx Adapter > from enqueueing any packets to the Tx queue. > > +* **Added initial LoongArch architecture support.** > + > + * Added EAL implementation for LoongArch architecture. The initial devices > + the porting was tested on included Loongson 3A5000, Loongson 3C5000 and > + Loongson 3C5000L. In theory this implementation should work with any target > + based on ``LoongArch`` ISA. > + This is a new feature in EAL. As described in the comments in the release notes, EAL features come first in the list. > > Removed Items > ------------- > diff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build > index 84fd42754e..16fd491b9a 100644 > --- a/drivers/net/i40e/meson.build > +++ b/drivers/net/i40e/meson.build > @@ -7,6 +7,12 @@ if arch_subdir == 'riscv' > subdir_done() > endif > > +if arch_subdir == 'loongarch' > + build = false > + reason = 'not supported on LoongArch' > + subdir_done() > +endif > + > cflags += ['-DPF_DRIVER', > '-DVF_DRIVER', > '-DINTEGRATED_VF', > diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build > index a18908ef7c..80ab012448 100644 > --- a/drivers/net/ixgbe/meson.build > +++ b/drivers/net/ixgbe/meson.build > @@ -1,6 +1,12 @@ > # SPDX-License-Identifier: BSD-3-Clause > # Copyright(c) 2017 Intel Corporation > > +if arch_subdir == 'loongarch' > + build = false > + reason = 'not supported on LoongArch' > + subdir_done() > +endif > + > cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS'] > > subdir('base') > diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build > index 680bc8631c..30c0fbc798 100644 > --- a/drivers/net/memif/meson.build > +++ b/drivers/net/memif/meson.build > @@ -1,6 +1,12 @@ > # SPDX-License-Identifier: BSD-3-Clause > # Copyright 2018-2019 Cisco Systems, Inc. All rights reserved. > > +if arch_subdir == 'loongarch' > + build = false > + reason = 'not supported on LoongArch' > + subdir_done() > +endif > + > if not is_linux > build = false > reason = 'only supported on Linux' > diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build > index c09713a67b..f0d03069cd 100644 > --- a/drivers/net/tap/meson.build > +++ b/drivers/net/tap/meson.build > @@ -1,6 +1,12 @@ > # SPDX-License-Identifier: BSD-3-Clause > # Copyright 2018 Luca Boccassi <bluca@debian.org> > > +if arch_subdir == 'loongarch' > + build = false > + reason = 'not supported on LoongArch' > + subdir_done() > +endif > + > if not is_linux > build = false > reason = 'only supported on Linux' > diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build > index b40244a941..d2f2d96099 100644 > --- a/examples/l3fwd/meson.build > +++ b/examples/l3fwd/meson.build > @@ -6,6 +6,12 @@ > # To build this example as a standalone application with an already-installed > # DPDK instance, use 'make' > > +if arch_subdir == 'loongarch' > + build = false > + reason = 'not supported on LoongArch' > + subdir_done() > +endif > + > allow_experimental_apis = true > deps += ['acl', 'hash', 'lpm', 'fib', 'eventdev'] > sources = files( > diff --git a/lib/eal/linux/eal_memory.c b/lib/eal/linux/eal_memory.c > index c890c42106..60fc8cc6ca 100644 > --- a/lib/eal/linux/eal_memory.c > +++ b/lib/eal/linux/eal_memory.c > @@ -77,7 +77,11 @@ uint64_t eal_get_baseaddr(void) > * rte_mem_check_dma_mask for ensuring all memory is within supported > * range. > */ > +#if defined(RTE_ARCH_LOONGARCH) > + return 0x7000000000ULL; > +#else > return 0x100000000ULL; > +#endif > } > > /* > diff --git a/lib/eal/loongarch/include/meson.build b/lib/eal/loongarch/include/meson.build > new file mode 100644 > index 0000000000..6e8d12601a > --- /dev/null > +++ b/lib/eal/loongarch/include/meson.build > @@ -0,0 +1,18 @@ > +# SPDX-License-Identifier: BSD-3-Clause > +# Copyright(c) 2022 Loongson Technology Corporation Limited > + > +arch_headers = files( > + 'rte_atomic.h', > + 'rte_byteorder.h', > + 'rte_cpuflags.h', > + 'rte_cycles.h', > + 'rte_io.h', > + 'rte_memcpy.h', > + 'rte_pause.h', > + 'rte_power_intrinsics.h', > + 'rte_prefetch.h', > + 'rte_rwlock.h', > + 'rte_spinlock.h', > + 'rte_vect.h', > +) > +install_headers(arch_headers, subdir: get_option('include_subdir_arch')) > diff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h > new file mode 100644 > index 0000000000..b0ddcab72e > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_atomic.h > @@ -0,0 +1,47 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_ATOMIC_LOONGARCH_H_ > +#define _RTE_ATOMIC_LOONGARCH_H_ No need for _. RTE_ATOMIC_LOONGARCH_H is enough. This comment applies to other headers. > + > +#ifndef RTE_FORCE_INTRINSICS > +# error Platform must be built with RTE_FORCE_INTRINSICS > +#endif > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include <rte_common.h> > +#include "generic/rte_atomic.h" > + > +#define rte_mb() do { asm volatile("dbar 0":::"memory"); } while (0) > + > +#define rte_wmb() rte_mb() > + > +#define rte_rmb() rte_mb() > + > +#define rte_smp_mb() rte_mb() > + > +#define rte_smp_wmb() rte_mb() > + > +#define rte_smp_rmb() rte_mb() > + > +#define rte_io_mb() rte_mb() > + > +#define rte_io_wmb() rte_mb() > + > +#define rte_io_rmb() rte_mb() > + > +static __rte_always_inline void > +rte_atomic_thread_fence(int memorder) > +{ > + __atomic_thread_fence(memorder); > +} > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_ATOMIC_LOONGARCH_H_ */ > diff --git a/lib/eal/loongarch/include/rte_byteorder.h b/lib/eal/loongarch/include/rte_byteorder.h > new file mode 100644 > index 0000000000..ba27998497 > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_byteorder.h > @@ -0,0 +1,40 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_BYTEORDER_LOONGARCH_H_ > +#define _RTE_BYTEORDER_LOONGARCH_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include "generic/rte_byteorder.h" > + > +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN > + > +#define rte_cpu_to_le_16(x) (x) > +#define rte_cpu_to_le_32(x) (x) > +#define rte_cpu_to_le_64(x) (x) > + > +#define rte_cpu_to_be_16(x) rte_bswap16(x) > +#define rte_cpu_to_be_32(x) rte_bswap32(x) > +#define rte_cpu_to_be_64(x) rte_bswap64(x) > + > +#define rte_le_to_cpu_16(x) (x) > +#define rte_le_to_cpu_32(x) (x) > +#define rte_le_to_cpu_64(x) (x) > + > +#define rte_be_to_cpu_16(x) rte_bswap16(x) > +#define rte_be_to_cpu_32(x) rte_bswap32(x) > +#define rte_be_to_cpu_64(x) rte_bswap64(x) > + > +#else /* RTE_BIG_ENDIAN */ > +#error "LoongArch not support big endian!" > +#endif > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_BYTEORDER_LOONGARCH_H_ */ > diff --git a/lib/eal/loongarch/include/rte_cpuflags.h b/lib/eal/loongarch/include/rte_cpuflags.h > new file mode 100644 > index 0000000000..d9121a00a8 > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_cpuflags.h > @@ -0,0 +1,39 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_CPUFLAGS_LOONGARCH_H_ > +#define _RTE_CPUFLAGS_LOONGARCH_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/** > + * Enumeration of all CPU features supported > + */ > +enum rte_cpu_flag_t { > + RTE_CPUFLAG_CPUCFG = 0, > + RTE_CPUFLAG_LAM, > + RTE_CPUFLAG_UAL, > + RTE_CPUFLAG_FPU, > + RTE_CPUFLAG_LSX, > + RTE_CPUFLAG_LASX, > + RTE_CPUFLAG_CRC32, > + RTE_CPUFLAG_COMPLEX, > + RTE_CPUFLAG_CRYPTO, > + RTE_CPUFLAG_LVZ, > + RTE_CPUFLAG_LBT_X86, > + RTE_CPUFLAG_LBT_ARM, > + RTE_CPUFLAG_LBT_MIPS, > + /* The last item */ > + RTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */ > +}; > + > +#include "generic/rte_cpuflags.h" > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_CPUFLAGS_LOONGARCH_H_ */ > diff --git a/lib/eal/loongarch/include/rte_cycles.h b/lib/eal/loongarch/include/rte_cycles.h > new file mode 100644 > index 0000000000..0f1539be1b > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_cycles.h > @@ -0,0 +1,47 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_CYCLES_LOONGARCH_H_ > +#define _RTE_CYCLES_LOONGARCH_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include "generic/rte_cycles.h" > + > +/** > + * Read the time base register. > + * > + * @return > + * The time base for this lcore. > + */ > +static inline uint64_t > +rte_rdtsc(void) > +{ > + uint64_t count; > + > + __asm__ __volatile__ ( > + "rdtime.d %[cycles], $zero\n" > + : [cycles] "=r" (count) > + :: > + ); > + return count; > +} > + > +static inline uint64_t > +rte_rdtsc_precise(void) > +{ > + rte_mb(); > + return rte_rdtsc(); > +} > + > +static inline uint64_t > +rte_get_tsc_cycles(void) { return rte_rdtsc(); } > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_CYCLES_LOONGARCH_H_ */ > diff --git a/lib/eal/loongarch/include/rte_io.h b/lib/eal/loongarch/include/rte_io.h > new file mode 100644 > index 0000000000..af152a727a > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_io.h > @@ -0,0 +1,18 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_IO_LOONGARCH_H_ > +#define _RTE_IO_LOONGARCH_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include "generic/rte_io.h" > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_IO_LOONGARCH_H_ */ > diff --git a/lib/eal/loongarch/include/rte_memcpy.h b/lib/eal/loongarch/include/rte_memcpy.h > new file mode 100644 > index 0000000000..e7b91e9ce4 > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_memcpy.h > @@ -0,0 +1,61 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_MEMCPY_LOONGARCH_H_ > +#define _RTE_MEMCPY_LOONGARCH_H_ > + > +#include <stdint.h> > +#include <string.h> > + > +#include "rte_common.h" > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include "generic/rte_memcpy.h" > + > +static inline void > +rte_mov16(uint8_t *dst, const uint8_t *src) > +{ > + memcpy(dst, src, 16); > +} > + > +static inline void > +rte_mov32(uint8_t *dst, const uint8_t *src) > +{ > + memcpy(dst, src, 32); > +} > + > +static inline void > +rte_mov48(uint8_t *dst, const uint8_t *src) > +{ > + memcpy(dst, src, 48); > +} > + > +static inline void > +rte_mov64(uint8_t *dst, const uint8_t *src) > +{ > + memcpy(dst, src, 64); > +} > + > +static inline void > +rte_mov128(uint8_t *dst, const uint8_t *src) > +{ > + memcpy(dst, src, 128); > +} > + > +static inline void > +rte_mov256(uint8_t *dst, const uint8_t *src) > +{ > + memcpy(dst, src, 256); > +} > + > +#define rte_memcpy(d, s, n) memcpy((d), (s), (n)) > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_MEMCPY_LOONGARCH_H_ */ > diff --git a/lib/eal/loongarch/include/rte_pause.h b/lib/eal/loongarch/include/rte_pause.h > new file mode 100644 > index 0000000000..438de23128 > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_pause.h > @@ -0,0 +1,24 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_PAUSE_LOONGARCH_H_ > +#define _RTE_PAUSE_LOONGARCH_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include "rte_atomic.h" > + > +#include "generic/rte_pause.h" > + > +static inline void rte_pause(void) > +{ > +} > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_PAUSE_LOONGARCH_H_ */ > diff --git a/lib/eal/loongarch/include/rte_power_intrinsics.h b/lib/eal/loongarch/include/rte_power_intrinsics.h > new file mode 100644 > index 0000000000..b6a2c0d82e > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_power_intrinsics.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_POWER_INTRINSIC_LOONGARCH_H_ > +#define _RTE_POWER_INTRINSIC_LOONGARCH_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include <rte_common.h> > + > +#include "generic/rte_power_intrinsics.h" > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_POWER_INTRINSIC_LOONGARCH_H_ */ > diff --git a/lib/eal/loongarch/include/rte_prefetch.h b/lib/eal/loongarch/include/rte_prefetch.h > new file mode 100644 > index 0000000000..0fd9262ea8 > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_prefetch.h > @@ -0,0 +1,47 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_PREFETCH_LOONGARCH_H_ > +#define _RTE_PREFETCH_LOONGARCH_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include <rte_common.h> > +#include "generic/rte_prefetch.h" > + > +static inline void rte_prefetch0(const volatile void *p) > +{ > + __builtin_prefetch((const void *)(uintptr_t)p, 0, 3); > +} > + > +static inline void rte_prefetch1(const volatile void *p) > +{ > + __builtin_prefetch((const void *)(uintptr_t)p, 0, 2); > +} > + > +static inline void rte_prefetch2(const volatile void *p) > +{ > + __builtin_prefetch((const void *)(uintptr_t)p, 0, 1); > +} > + > +static inline void rte_prefetch_non_temporal(const volatile void *p) > +{ > + /* non-temporal version not available, fallback to rte_prefetch0 */ > + rte_prefetch0(p); > +} > + > +__rte_experimental > +static inline void > +rte_cldemote(const volatile void *p) > +{ > + RTE_SET_USED(p); > +} > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_PREFETCH_LOONGARCH_H_ */ > diff --git a/lib/eal/loongarch/include/rte_rwlock.h b/lib/eal/loongarch/include/rte_rwlock.h > new file mode 100644 > index 0000000000..aac6f60120 > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_rwlock.h > @@ -0,0 +1,42 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_RWLOCK_LOONGARCH_H_ > +#define _RTE_RWLOCK_LOONGARCH_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include "generic/rte_rwlock.h" > + > +static inline void > +rte_rwlock_read_lock_tm(rte_rwlock_t *rwl) > +{ > + rte_rwlock_read_lock(rwl); > +} > + > +static inline void > +rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl) > +{ > + rte_rwlock_read_unlock(rwl); > +} > + > +static inline void > +rte_rwlock_write_lock_tm(rte_rwlock_t *rwl) > +{ > + rte_rwlock_write_lock(rwl); > +} > + > +static inline void > +rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl) > +{ > + rte_rwlock_write_unlock(rwl); > +} > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_RWLOCK_LOONGARCH_H_ */ > diff --git a/lib/eal/loongarch/include/rte_spinlock.h b/lib/eal/loongarch/include/rte_spinlock.h > new file mode 100644 > index 0000000000..dd07538c7f > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_spinlock.h > @@ -0,0 +1,64 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_SPINLOCK_LOONGARCH_H_ > +#define _RTE_SPINLOCK_LOONGARCH_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include <rte_common.h> > +#include "generic/rte_spinlock.h" > + > +#ifndef RTE_FORCE_INTRINSICS > +# error Platform must be built with RTE_FORCE_INTRINSICS > +#endif > + > +static inline int rte_tm_supported(void) > +{ > + return 0; > +} > + > +static inline void > +rte_spinlock_lock_tm(rte_spinlock_t *sl) > +{ > + rte_spinlock_lock(sl); /* fall-back */ > +} > + > +static inline int > +rte_spinlock_trylock_tm(rte_spinlock_t *sl) > +{ > + return rte_spinlock_trylock(sl); > +} > + > +static inline void > +rte_spinlock_unlock_tm(rte_spinlock_t *sl) > +{ > + rte_spinlock_unlock(sl); > +} > + > +static inline void > +rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr) > +{ > + rte_spinlock_recursive_lock(slr); /* fall-back */ > +} > + > +static inline void > +rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr) > +{ > + rte_spinlock_recursive_unlock(slr); > +} > + > +static inline int > +rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr) > +{ > + return rte_spinlock_recursive_trylock(slr); > +} > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_SPINLOCK_LOONGARCH_H_ */ > diff --git a/lib/eal/loongarch/include/rte_vect.h b/lib/eal/loongarch/include/rte_vect.h > new file mode 100644 > index 0000000000..5951a2674c > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_vect.h > @@ -0,0 +1,65 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_VECT_LOONGARCH_H_ > +#define _RTE_VECT_LOONGARCH_H_ > + > +#include <stdint.h> > +#include "generic/rte_vect.h" > +#include "rte_common.h" > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED > + > +typedef union xmm { > + int8_t i8[16]; > + int16_t i16[8]; > + int32_t i32[4]; > + int64_t i64[2]; > + uint8_t u8[16]; > + uint16_t u16[8]; > + uint32_t u32[4]; > + uint64_t u64[2]; > + double pd[2]; > +} __rte_aligned(16) xmm_t; > + > +#define XMM_SIZE (sizeof(xmm_t)) > +#define XMM_MASK (XMM_SIZE - 1) > + > +typedef union rte_xmm { > + xmm_t x; > + uint8_t u8[XMM_SIZE / sizeof(uint8_t)]; > + uint16_t u16[XMM_SIZE / sizeof(uint16_t)]; > + uint32_t u32[XMM_SIZE / sizeof(uint32_t)]; > + uint64_t u64[XMM_SIZE / sizeof(uint64_t)]; > + double pd[XMM_SIZE / sizeof(double)]; > +} __rte_aligned(16) rte_xmm_t; > + > +static inline xmm_t > +vect_load_128(void *p) > +{ > + xmm_t ret = *((xmm_t *)p); > + > + return ret; > +} > + > +static inline xmm_t > +vect_and(xmm_t data, xmm_t mask) > +{ > + rte_xmm_t ret = {.x = data }; > + rte_xmm_t m = {.x = mask }; > + ret.u64[0] &= m.u64[0]; > + ret.u64[1] &= m.u64[1]; > + > + return ret.x; > +} > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif > diff --git a/lib/eal/loongarch/meson.build b/lib/eal/loongarch/meson.build > new file mode 100644 > index 0000000000..4dcc27babb > --- /dev/null > +++ b/lib/eal/loongarch/meson.build > @@ -0,0 +1,11 @@ > +# SPDX-License-Identifier: BSD-3-Clause > +# Copyright(c) 2022 Loongson Technology Corporation Limited > + > +subdir('include') > + > +sources += files( > + 'rte_cpuflags.c', > + 'rte_cycles.c', > + 'rte_hypervisor.c', > + 'rte_power_intrinsics.c', > +) > diff --git a/lib/eal/loongarch/rte_cpuflags.c b/lib/eal/loongarch/rte_cpuflags.c > new file mode 100644 > index 0000000000..0a75ca58d4 > --- /dev/null > +++ b/lib/eal/loongarch/rte_cpuflags.c > @@ -0,0 +1,93 @@ > +/* > + * SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#include "rte_cpuflags.h" > + > +#include <elf.h> > +#include <fcntl.h> > +#include <assert.h> > +#include <unistd.h> > +#include <string.h> > + > +/* Symbolic values for the entries in the auxiliary table */ > +#define AT_HWCAP 16 > + > +/* software based registers */ > +enum cpu_register_t { > + REG_NONE = 0, > + REG_HWCAP, > + REG_MAX > +}; > + > +typedef uint32_t hwcap_registers_t[REG_MAX]; > + > +struct feature_entry { > + uint32_t reg; > + uint32_t bit; > +#define CPU_FLAG_NAME_MAX_LEN 64 > + char name[CPU_FLAG_NAME_MAX_LEN]; > +}; > + > +#define FEAT_DEF(name, reg, bit) \ > + [RTE_CPUFLAG_##name] = {reg, bit, #name}, > + > +const struct feature_entry rte_cpu_feature_table[] = { > + FEAT_DEF(CPUCFG, REG_HWCAP, 0) > + FEAT_DEF(LAM, REG_HWCAP, 1) > + FEAT_DEF(UAL, REG_HWCAP, 2) > + FEAT_DEF(FPU, REG_HWCAP, 3) > + FEAT_DEF(LSX, REG_HWCAP, 4) > + FEAT_DEF(LASX, REG_HWCAP, 5) > + FEAT_DEF(CRC32, REG_HWCAP, 6) > + FEAT_DEF(COMPLEX, REG_HWCAP, 7) > + FEAT_DEF(CRYPTO, REG_HWCAP, 8) > + FEAT_DEF(LVZ, REG_HWCAP, 9) > + FEAT_DEF(LBT_X86, REG_HWCAP, 10) > + FEAT_DEF(LBT_ARM, REG_HWCAP, 11) > + FEAT_DEF(LBT_MIPS, REG_HWCAP, 12) > +}; > + > +/* > + * Read AUXV software register and get cpu features for LoongArch > + */ > +static void > +rte_cpu_get_features(hwcap_registers_t out) > +{ > + out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); > +} > + > +/* > + * Checks if a particular flag is available on current machine. > + */ > +int > +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) > +{ > + const struct feature_entry *feat; > + hwcap_registers_t regs = {0}; > + > + if (feature >= RTE_CPUFLAG_NUMFLAGS) > + return -ENOENT; > + > + feat = &rte_cpu_feature_table[feature]; > + if (feat->reg == REG_NONE) > + return -EFAULT; > + > + rte_cpu_get_features(regs); > + return (regs[feat->reg] >> feat->bit) & 1; > +} > + > +const char * > +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) > +{ > + if (feature >= RTE_CPUFLAG_NUMFLAGS) > + return NULL; > + return rte_cpu_feature_table[feature].name; > +} > + > +void > +rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics) > +{ > + memset(intrinsics, 0, sizeof(*intrinsics)); > +} > diff --git a/lib/eal/loongarch/rte_cycles.c b/lib/eal/loongarch/rte_cycles.c > new file mode 100644 > index 0000000000..582601d335 > --- /dev/null > +++ b/lib/eal/loongarch/rte_cycles.c > @@ -0,0 +1,45 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#include "eal_private.h" > + > +#define LOONGARCH_CPUCFG4 0x4 > +#define CPUCFG4_CCFREQ_MASK 0xFFFFFFFF > +#define CPUCFG4_CCFREQ_SHIFT 0 > + > +#define LOONGARCH_CPUCFG5 0x5 > +#define CPUCFG5_CCMUL_MASK 0xFFFF > +#define CPUCFG5_CCMUL_SHIFT 0 > + > +#define CPUCFG5_CCDIV_MASK 0xFFFF0000 > +#define CPUCFG5_CCDIV_SHIFT 16 > + > +static __rte_noinline uint32_t > +read_cpucfg(int arg) > +{ > + int ret = 0; > + > + __asm__ __volatile__ ( > + "cpucfg %[var], %[index]\n" > + : [var]"=r"(ret) > + : [index]"r"(arg) > + : > + ); > + > + return ret; > +} > + > +uint64_t > +get_tsc_freq_arch(void) > +{ > + uint32_t base_freq, mul_factor, div_factor; > + > + base_freq = read_cpucfg(LOONGARCH_CPUCFG4); > + mul_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCMUL_MASK) >> > + CPUCFG5_CCMUL_SHIFT; > + div_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCDIV_MASK) >> > + CPUCFG5_CCDIV_SHIFT; > + > + return base_freq * mul_factor / div_factor; > +} > diff --git a/lib/eal/loongarch/rte_hypervisor.c b/lib/eal/loongarch/rte_hypervisor.c > new file mode 100644 > index 0000000000..d044906f71 > --- /dev/null > +++ b/lib/eal/loongarch/rte_hypervisor.c > @@ -0,0 +1,11 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#include "rte_hypervisor.h" > + > +enum rte_hypervisor > +rte_hypervisor_get(void) > +{ > + return RTE_HYPERVISOR_UNKNOWN; > +} > diff --git a/lib/eal/loongarch/rte_power_intrinsics.c b/lib/eal/loongarch/rte_power_intrinsics.c > new file mode 100644 > index 0000000000..a8969c260e > --- /dev/null > +++ b/lib/eal/loongarch/rte_power_intrinsics.c > @@ -0,0 +1,53 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#include <errno.h> > + > +#include "rte_power_intrinsics.h" > + > +/** > + * This function is not supported on LOONGARCH. > + */ > +int > +rte_power_monitor(const struct rte_power_monitor_cond *pmc, > + const uint64_t tsc_timestamp) > +{ > + RTE_SET_USED(pmc); > + RTE_SET_USED(tsc_timestamp); > + > + return -ENOTSUP; > +} > + > +/** > + * This function is not supported on LOONGARCH. > + */ > +int > +rte_power_pause(const uint64_t tsc_timestamp) > +{ > + RTE_SET_USED(tsc_timestamp); > + > + return -ENOTSUP; > +} > + > +/** > + * This function is not supported on LOONGARCH. > + */ > +int > +rte_power_monitor_wakeup(const unsigned int lcore_id) > +{ > + RTE_SET_USED(lcore_id); > + > + return -ENOTSUP; > +} > + > +int > +rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[], > + const uint32_t num, const uint64_t tsc_timestamp) > +{ > + RTE_SET_USED(pmc); > + RTE_SET_USED(num); > + RTE_SET_USED(tsc_timestamp); > + > + return -ENOTSUP; > +} > diff --git a/meson.build b/meson.build > index 7d6643da3a..de718974d4 100644 > --- a/meson.build > +++ b/meson.build > @@ -56,6 +56,8 @@ elif host_machine.cpu_family().startswith('ppc') > arch_subdir = 'ppc' > elif host_machine.cpu_family().startswith('riscv') > arch_subdir = 'riscv' > +elif host_machine.cpu_family().startswith('loongarch') > + arch_subdir = 'loongarch' > endif Please insert it earlier, between arm and ppc. -- David Marchand ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v7 1/7] eal/loongarch: support LoongArch architecture 2022-10-03 17:15 ` David Marchand @ 2022-10-04 8:49 ` zhoumin 0 siblings, 0 replies; 20+ messages in thread From: zhoumin @ 2022-10-04 8:49 UTC (permalink / raw) To: David Marchand Cc: thomas, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo Hi, David, Thanks a lot for your helpful reply. On Tue, Oct 4, 2022 at 01:15, David Marchand wrote: > On Fri, Sep 30, 2022 at 10:02 AM Min Zhou <zhoumin@loongson.cn> wrote: >> Add all necessary elements for DPDK to compile and run EAL on >> LoongArch64 Soc. >> >> This includes: >> >> - EAL library implementation for LoongArch ISA. >> - meson build structure for 'loongarch' architecture. >> RTE_ARCH_LOONGARCH define is added for architecture identification. >> - xmm_t structure operation stubs as there is no vector support in >> the current version for LoongArch. >> >> Compilation was tested on Debian and CentOS using loongarch64 >> cross-compile toolchain from x86 build hosts. Functions were tested >> on Loongnix and Kylin which are two Linux distributions supported >> LoongArch host based on Linux 4.19 maintained by Loongson >> Corporation. >> >> We also tested DPDK on LoongArch with some external applications, >> including: Pktgen-DPDK, OVS, VPP. >> >> The platform is currently marked as linux-only because there is no >> other OS than Linux support LoongArch host currently. >> >> The i40e PMD driver is disabled on LoongArch because of the absence >> of vector support in the current version. >> >> Similar to RISC-V, the compilation of following modules has been >> disabled by this commit and will be re-enabled in later commits as >> fixes are introduced: >> net/ixgbe, net/memif, net/tap, example/l3fwd. >> >> Signed-off-by: Min Zhou <zhoumin@loongson.cn> >> --- >> MAINTAINERS | 6 ++ >> app/test/test_xmmt_ops.h | 12 +++ >> .../loongarch/loongarch_loongarch64_linux_gcc | 16 ++++ >> config/loongarch/meson.build | 43 +++++++++ > Please update devtools/test-meson-builds.sh in this patch. > > I tested the compilation of the series per patch (I caught one issue > in net/bnxt which I posted a fix for), with this diff: > > @@ -260,6 +260,10 @@ build build-x86-mingw $f skipABI -Dexamples=helloworld > f=$srcdir/config/arm/arm64_armv8_linux_gcc > build build-arm64-generic-gcc $f ABI $use_shared > > +# generic LoongArch > +f=$srcdir/config/loongarch/loongarch_loongarch64_linux_gcc > +build build-loongarch64-generic-gcc $f ABI $use_shared > + > # IBM POWER > f=$srcdir/config/ppc/ppc64le-power8-linux-gcc > build build-ppc64-power8-gcc $f ABI $use_shared OK, thanks. It's very helpful. I ever tried to add them, but I ran into some problems during the test. I will add them into the v8 patchset. > >> doc/guides/contributing/design.rst | 2 +- >> .../cross_build_dpdk_for_loongarch.rst | 87 +++++++++++++++++ >> doc/guides/linux_gsg/index.rst | 1 + >> doc/guides/nics/features.rst | 8 ++ >> doc/guides/nics/features/default.ini | 1 + >> doc/guides/rel_notes/release_22_11.rst | 7 ++ >> drivers/net/i40e/meson.build | 6 ++ >> drivers/net/ixgbe/meson.build | 6 ++ >> drivers/net/memif/meson.build | 6 ++ >> drivers/net/tap/meson.build | 6 ++ >> examples/l3fwd/meson.build | 6 ++ >> lib/eal/linux/eal_memory.c | 4 + >> lib/eal/loongarch/include/meson.build | 18 ++++ >> lib/eal/loongarch/include/rte_atomic.h | 47 ++++++++++ >> lib/eal/loongarch/include/rte_byteorder.h | 40 ++++++++ >> lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++ >> lib/eal/loongarch/include/rte_cycles.h | 47 ++++++++++ >> lib/eal/loongarch/include/rte_io.h | 18 ++++ >> lib/eal/loongarch/include/rte_memcpy.h | 61 ++++++++++++ >> lib/eal/loongarch/include/rte_pause.h | 24 +++++ >> .../loongarch/include/rte_power_intrinsics.h | 20 ++++ >> lib/eal/loongarch/include/rte_prefetch.h | 47 ++++++++++ >> lib/eal/loongarch/include/rte_rwlock.h | 42 +++++++++ >> lib/eal/loongarch/include/rte_spinlock.h | 64 +++++++++++++ >> lib/eal/loongarch/include/rte_vect.h | 65 +++++++++++++ >> lib/eal/loongarch/meson.build | 11 +++ >> lib/eal/loongarch/rte_cpuflags.c | 93 +++++++++++++++++++ >> lib/eal/loongarch/rte_cycles.c | 45 +++++++++ >> lib/eal/loongarch/rte_hypervisor.c | 11 +++ >> lib/eal/loongarch/rte_power_intrinsics.c | 53 +++++++++++ >> meson.build | 2 + >> 35 files changed, 963 insertions(+), 1 deletion(-) >> create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc >> create mode 100644 config/loongarch/meson.build >> create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst >> create mode 100644 lib/eal/loongarch/include/meson.build >> create mode 100644 lib/eal/loongarch/include/rte_atomic.h >> create mode 100644 lib/eal/loongarch/include/rte_byteorder.h >> create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h >> create mode 100644 lib/eal/loongarch/include/rte_cycles.h >> create mode 100644 lib/eal/loongarch/include/rte_io.h >> create mode 100644 lib/eal/loongarch/include/rte_memcpy.h >> create mode 100644 lib/eal/loongarch/include/rte_pause.h >> create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h >> create mode 100644 lib/eal/loongarch/include/rte_prefetch.h >> create mode 100644 lib/eal/loongarch/include/rte_rwlock.h >> create mode 100644 lib/eal/loongarch/include/rte_spinlock.h >> create mode 100644 lib/eal/loongarch/include/rte_vect.h >> create mode 100644 lib/eal/loongarch/meson.build >> create mode 100644 lib/eal/loongarch/rte_cpuflags.c >> create mode 100644 lib/eal/loongarch/rte_cycles.c >> create mode 100644 lib/eal/loongarch/rte_hypervisor.c >> create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 51d77460ec..6c5fcef749 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -294,6 +294,12 @@ F: app/*/*_neon.* >> F: examples/*/*_neon.* >> F: examples/common/neon/ >> >> +LoongArch >> +M: Min Zhou <zhoumin@loongson.cn> >> +F: config/loongarch/ >> +F: doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst >> +F: lib/eal/loongarch/ >> + >> IBM POWER (alpha) >> M: David Christensen <drc@linux.vnet.ibm.com> >> F: config/ppc/ >> diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h >> index 55f256599e..626aa9bcba 100644 >> --- a/app/test/test_xmmt_ops.h >> +++ b/app/test/test_xmmt_ops.h >> @@ -65,6 +65,18 @@ vect_set_epi32(int i3, int i2, int i1, int i0) >> return data; >> } >> >> +#elif defined(RTE_ARCH_LOONGARCH) >> + >> +#define vect_loadu_sil128(p) vect_load_128(p) >> + >> +/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */ >> +static __rte_always_inline xmm_t >> +vect_set_epi32(int i3, int i2, int i1, int i0) >> +{ >> + xmm_t data = (xmm_t){.u32 = {i0, i1, i2, i3}}; >> + >> + return data; >> +} >> #endif >> >> #endif /* _TEST_XMMT_OPS_H_ */ >> diff --git a/config/loongarch/loongarch_loongarch64_linux_gcc b/config/loongarch/loongarch_loongarch64_linux_gcc >> new file mode 100644 >> index 0000000000..0c44ae96e6 >> --- /dev/null >> +++ b/config/loongarch/loongarch_loongarch64_linux_gcc >> @@ -0,0 +1,16 @@ >> +[binaries] >> +c = 'loongarch64-unknown-linux-gnu-gcc' >> +cpp = 'loongarch64-unknown-linux-gnu-cpp' >> +ar = 'loongarch64-unknown-linux-gnu-gcc-ar' >> +strip = 'loongarch64-unknown-linux-gnu-strip' >> +pcap-config = '' >> + >> +[host_machine] >> +system = 'linux' >> +cpu_family = 'loongarch64' >> +cpu = '3a5000' >> +endian = 'little' >> + >> +[properties] >> +implementor_id = 'generic' >> +implementor_pn = 'default' > Two things to fix here: > - Please add ccache, see e3fd286ec471 ("build: add ccache for cross > compilation") > - the cpp meson variable should refer to a c++ compiler. See > f75dd6d3b121 ("config: fix C++ cross compiler for Arm and PPC") OK, thanks. I will add "ccache" into the build configuration file for LoongArch and test it. > >> diff --git a/config/loongarch/meson.build b/config/loongarch/meson.build >> new file mode 100644 >> index 0000000000..99dabef203 >> --- /dev/null >> +++ b/config/loongarch/meson.build >> @@ -0,0 +1,43 @@ >> +# SPDX-License-Identifier: BSD-3-Clause >> +# Copyright(c) 2022 Loongson Technology Corporation Limited >> + >> +if not dpdk_conf.get('RTE_ARCH_64') >> + error('Only 64-bit compiles are supported for this platform type') >> +endif >> +dpdk_conf.set('RTE_ARCH', 'loongarch') >> +dpdk_conf.set('RTE_ARCH_LOONGARCH', 1) >> +dpdk_conf.set('RTE_FORCE_INTRINSICS', 1) >> + >> +machine_args_generic = [ >> + ['default', ['-march=loongarch64']], >> +] >> + >> +flags_generic = [ >> + ['RTE_MACHINE', '"loongarch64"'], >> + ['RTE_MAX_LCORE', 64], >> + ['RTE_MAX_NUMA_NODES', 16], >> + ['RTE_CACHE_LINE_SIZE', 64]] >> + >> +impl_generic = ['Generic loongarch', flags_generic, machine_args_generic] >> + >> +machine = [] >> +machine_args = [] >> + >> +machine = impl_generic >> +impl_pn = 'default' >> + >> +message('Implementer : ' + machine[0]) >> +foreach flag: machine[1] >> + if flag.length() > 0 >> + dpdk_conf.set(flag[0], flag[1]) >> + endif >> +endforeach >> + >> +foreach marg: machine[2] >> + if marg[0] == impl_pn >> + foreach f: marg[1] >> + machine_args += f >> + endforeach >> + endif >> +endforeach >> +message(machine_args) > > cpu_instruction_set is not supported, though I am not sure LoongArch needs it. > Maybe something to add in the future but not blocking atm. OK, thanks. I will check the "cpu_instruction_set" option for LoongArch. Maybe it's better to add it at the initial commit. > >> diff --git a/doc/guides/contributing/design.rst b/doc/guides/contributing/design.rst >> index 0383afe5c8..d24a7ff6a0 100644 >> --- a/doc/guides/contributing/design.rst >> +++ b/doc/guides/contributing/design.rst >> @@ -42,7 +42,7 @@ Per Architecture Sources >> The following macro options can be used: >> >> * ``RTE_ARCH`` is a string that contains the name of the architecture. >> -* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures. >> +* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_LOONGARCH``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures. >> >> Per Execution Environment Sources >> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst >> new file mode 100644 >> index 0000000000..3afc6d4933 >> --- /dev/null >> +++ b/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst >> @@ -0,0 +1,87 @@ >> +.. SPDX-License-Identifier: BSD-3-Clause >> + Copyright(c) 2022 Loongson Technology Corporation Limited >> + >> +Cross compiling DPDK for LoongArch >> +================================== >> + >> +This chapter describes how to cross compile DPDK for LoongArch from x86 build >> +hosts. >> + >> +.. note:: >> + >> + Due to some of the code under review, the current Linux 5.19 cannot boot >> + on LoongArch system. There are still some Linux distributions that have >> + supported LoongArch host, such as Anolis OS, Kylin, Loongnix and UOS. These >> + distributions base on Linux kernel 4.19 supported by Loongson Corporation. >> + Because LoongArch is such a new platform with many fundamental pieces of >> + software still under development, it is currently recommended to cross >> + compile DPDK on x86 for LoongArch. >> + >> + >> +Prerequisites >> +------------- >> + >> +Ensure that you have all pre-requisites for building DPDK natively as those >> +will be required also for cross-compilation. >> + >> +Linux kernel >> +~~~~~~~~~~~~ >> + >> +Make sure that LoongArch host is running Linux kernel 4.19 or newer supported >> +by Loongson Corporation. The support for LoongArch in the current Linux 5.19 >> +is not complete because it still misses some patches to add for other >> +subsystems. >> + >> +GNU toolchain >> +------------- >> + >> +Obtain the cross toolchain >> +~~~~~~~~~~~~~~~~~~~~~~~~~~ >> + >> +The build process was tested using: >> + >> +* Latest `LoongArch GNU toolchain >> + <https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz>`_ >> + on Debian 10.4 or CentOS 8. >> + >> +Alternatively the toolchain may be built straight from the source via CLFS, to >> +do that follow the instructions on `CLFS for LoongArch64 >> +<https://github.com/sunhaiyong1978/CLFS-for-LoongArch>`_ github page. >> + >> +To download cross tools from github we can use the following command: >> + >> +.. code-block:: console >> + >> + wget -P /tmp/ https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz >> + > Some people (like me ;-)) will want to generate their own cross toolchain. > I tried your script, and I added some comments in the thread where you > provided it. > > I think adding the whole script in the documentation is too much. > I would lean to adding a link to this thread in the documentation instead. > https://inbox.dpdk.org/dev/53b50799-cb29-7ee6-be89-4fe21566e127@loongson.cn/T/#m1da99578f85894a4ddcd8e39d8239869e6a501d1 > > Opinion? > OK, thanks. I also think it's a better way to add the link of this thread into the documentation and give some appropriate instructions. >> +Unzip and add into the PATH >> +~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> + >> +After downloading the cross-tools file, we need unzip and add those executable >> +binaries into the PATH as follows: >> + >> +.. code-block:: console >> + >> + tar -xvf /tmp/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz -C <cross_tool_install_dir> --strip-components 1 >> + export PATH=$PATH:<cross_tool_install_dir>/bin >> + >> + >> +Cross Compiling DPDK with GNU toolchain using Meson >> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> + >> +To cross-compile DPDK for generic LoongArch we can use the following command: >> + >> +.. code-block:: console >> + >> + meson cross-build --cross-file config/loongarch/loongarch_loongarch64_linux_gcc >> + ninja -C cross-build >> + >> +Supported cross-compilation targets >> +----------------------------------- >> + >> +Currently the following target is supported: >> + >> +* Generic LoongArch64 ISA: ``config/loongarch/loongarch_loongarch64_linux_gcc`` >> + >> +To add a new target support, a corresponding cross-file has to be added to >> +``config/loongarch`` directory. >> diff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst >> index 747552c385..c3e67bf9ec 100644 >> --- a/doc/guides/linux_gsg/index.rst >> +++ b/doc/guides/linux_gsg/index.rst >> @@ -14,6 +14,7 @@ Getting Started Guide for Linux >> sys_reqs >> build_dpdk >> cross_build_dpdk_for_arm64 >> + cross_build_dpdk_for_loongarch >> cross_build_dpdk_for_riscv >> linux_drivers >> build_sample_apps >> diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst >> index b4a8e9881c..2472049095 100644 >> --- a/doc/guides/nics/features.rst >> +++ b/doc/guides/nics/features.rst >> @@ -832,6 +832,14 @@ ARMv8 >> Support armv8a (64bit) architecture. >> >> >> +.. _nic_features_loongarch64: > Hum, one comment. > This is not related to your patch, so you can keep as you posted. > > Those anchors are unused, we should remove them all. OK, thanks. I will remove the added items. > >> + >> +LoongArch64 >> +----------- >> + >> +Support 64-bit LoongArch architecture. >> + >> + >> .. _nic_features_power8: >> >> Power8 >> diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini >> index f7192cb0da..cbc17c0434 100644 >> --- a/doc/guides/nics/features/default.ini >> +++ b/doc/guides/nics/features/default.ini >> @@ -71,6 +71,7 @@ Linux = >> Windows = >> ARMv7 = >> ARMv8 = >> +LoongArch64 = >> Power8 = >> rv64 = >> x86-32 = >> diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst >> index 0b4740abd1..ac1f9a924c 100644 >> --- a/doc/guides/rel_notes/release_22_11.rst >> +++ b/doc/guides/rel_notes/release_22_11.rst >> @@ -96,6 +96,13 @@ New Features >> * Added ``rte_event_eth_tx_adapter_queue_stop`` to stop the Tx Adapter >> from enqueueing any packets to the Tx queue. >> >> +* **Added initial LoongArch architecture support.** >> + >> + * Added EAL implementation for LoongArch architecture. The initial devices >> + the porting was tested on included Loongson 3A5000, Loongson 3C5000 and >> + Loongson 3C5000L. In theory this implementation should work with any target >> + based on ``LoongArch`` ISA. >> + > This is a new feature in EAL. > As described in the comments in the release notes, EAL features come > first in the list. > OK, thanks. It's my fault. I will fix this problem in the v8 patchset. >> Removed Items >> ------------- >> diff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build >> index 84fd42754e..16fd491b9a 100644 >> --- a/drivers/net/i40e/meson.build >> +++ b/drivers/net/i40e/meson.build >> @@ -7,6 +7,12 @@ if arch_subdir == 'riscv' >> subdir_done() >> endif >> >> +if arch_subdir == 'loongarch' >> + build = false >> + reason = 'not supported on LoongArch' >> + subdir_done() >> +endif >> + >> cflags += ['-DPF_DRIVER', >> '-DVF_DRIVER', >> '-DINTEGRATED_VF', >> diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build >> index a18908ef7c..80ab012448 100644 >> --- a/drivers/net/ixgbe/meson.build >> +++ b/drivers/net/ixgbe/meson.build >> @@ -1,6 +1,12 @@ >> # SPDX-License-Identifier: BSD-3-Clause >> # Copyright(c) 2017 Intel Corporation >> >> +if arch_subdir == 'loongarch' >> + build = false >> + reason = 'not supported on LoongArch' >> + subdir_done() >> +endif >> + >> cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS'] >> >> subdir('base') >> diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build >> index 680bc8631c..30c0fbc798 100644 >> --- a/drivers/net/memif/meson.build >> +++ b/drivers/net/memif/meson.build >> @@ -1,6 +1,12 @@ >> # SPDX-License-Identifier: BSD-3-Clause >> # Copyright 2018-2019 Cisco Systems, Inc. All rights reserved. >> >> +if arch_subdir == 'loongarch' >> + build = false >> + reason = 'not supported on LoongArch' >> + subdir_done() >> +endif >> + >> if not is_linux >> build = false >> reason = 'only supported on Linux' >> diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build >> index c09713a67b..f0d03069cd 100644 >> --- a/drivers/net/tap/meson.build >> +++ b/drivers/net/tap/meson.build >> @@ -1,6 +1,12 @@ >> # SPDX-License-Identifier: BSD-3-Clause >> # Copyright 2018 Luca Boccassi <bluca@debian.org> >> >> +if arch_subdir == 'loongarch' >> + build = false >> + reason = 'not supported on LoongArch' >> + subdir_done() >> +endif >> + >> if not is_linux >> build = false >> reason = 'only supported on Linux' >> diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build >> index b40244a941..d2f2d96099 100644 >> --- a/examples/l3fwd/meson.build >> +++ b/examples/l3fwd/meson.build >> @@ -6,6 +6,12 @@ >> # To build this example as a standalone application with an already-installed >> # DPDK instance, use 'make' >> >> +if arch_subdir == 'loongarch' >> + build = false >> + reason = 'not supported on LoongArch' >> + subdir_done() >> +endif >> + >> allow_experimental_apis = true >> deps += ['acl', 'hash', 'lpm', 'fib', 'eventdev'] >> sources = files( >> diff --git a/lib/eal/linux/eal_memory.c b/lib/eal/linux/eal_memory.c >> index c890c42106..60fc8cc6ca 100644 >> --- a/lib/eal/linux/eal_memory.c >> +++ b/lib/eal/linux/eal_memory.c >> @@ -77,7 +77,11 @@ uint64_t eal_get_baseaddr(void) >> * rte_mem_check_dma_mask for ensuring all memory is within supported >> * range. >> */ >> +#if defined(RTE_ARCH_LOONGARCH) >> + return 0x7000000000ULL; >> +#else >> return 0x100000000ULL; >> +#endif >> } >> >> /* >> diff --git a/lib/eal/loongarch/include/meson.build b/lib/eal/loongarch/include/meson.build >> new file mode 100644 >> index 0000000000..6e8d12601a >> --- /dev/null >> +++ b/lib/eal/loongarch/include/meson.build >> @@ -0,0 +1,18 @@ >> +# SPDX-License-Identifier: BSD-3-Clause >> +# Copyright(c) 2022 Loongson Technology Corporation Limited >> + >> +arch_headers = files( >> + 'rte_atomic.h', >> + 'rte_byteorder.h', >> + 'rte_cpuflags.h', >> + 'rte_cycles.h', >> + 'rte_io.h', >> + 'rte_memcpy.h', >> + 'rte_pause.h', >> + 'rte_power_intrinsics.h', >> + 'rte_prefetch.h', >> + 'rte_rwlock.h', >> + 'rte_spinlock.h', >> + 'rte_vect.h', >> +) >> +install_headers(arch_headers, subdir: get_option('include_subdir_arch')) >> diff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h >> new file mode 100644 >> index 0000000000..b0ddcab72e >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_atomic.h >> @@ -0,0 +1,47 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_ATOMIC_LOONGARCH_H_ >> +#define _RTE_ATOMIC_LOONGARCH_H_ > No need for _. > RTE_ATOMIC_LOONGARCH_H is enough. > > This comment applies to other headers. OK, thanks. I will check all added headers and fix them in the v8 patchset. >> + >> +#ifndef RTE_FORCE_INTRINSICS >> +# error Platform must be built with RTE_FORCE_INTRINSICS >> +#endif >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include <rte_common.h> >> +#include "generic/rte_atomic.h" >> + >> +#define rte_mb() do { asm volatile("dbar 0":::"memory"); } while (0) >> + >> +#define rte_wmb() rte_mb() >> + >> +#define rte_rmb() rte_mb() >> + >> +#define rte_smp_mb() rte_mb() >> + >> +#define rte_smp_wmb() rte_mb() >> + >> +#define rte_smp_rmb() rte_mb() >> + >> +#define rte_io_mb() rte_mb() >> + >> +#define rte_io_wmb() rte_mb() >> + >> +#define rte_io_rmb() rte_mb() >> + >> +static __rte_always_inline void >> +rte_atomic_thread_fence(int memorder) >> +{ >> + __atomic_thread_fence(memorder); >> +} >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_ATOMIC_LOONGARCH_H_ */ >> diff --git a/lib/eal/loongarch/include/rte_byteorder.h b/lib/eal/loongarch/include/rte_byteorder.h >> new file mode 100644 >> index 0000000000..ba27998497 >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_byteorder.h >> @@ -0,0 +1,40 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_BYTEORDER_LOONGARCH_H_ >> +#define _RTE_BYTEORDER_LOONGARCH_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include "generic/rte_byteorder.h" >> + >> +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN >> + >> +#define rte_cpu_to_le_16(x) (x) >> +#define rte_cpu_to_le_32(x) (x) >> +#define rte_cpu_to_le_64(x) (x) >> + >> +#define rte_cpu_to_be_16(x) rte_bswap16(x) >> +#define rte_cpu_to_be_32(x) rte_bswap32(x) >> +#define rte_cpu_to_be_64(x) rte_bswap64(x) >> + >> +#define rte_le_to_cpu_16(x) (x) >> +#define rte_le_to_cpu_32(x) (x) >> +#define rte_le_to_cpu_64(x) (x) >> + >> +#define rte_be_to_cpu_16(x) rte_bswap16(x) >> +#define rte_be_to_cpu_32(x) rte_bswap32(x) >> +#define rte_be_to_cpu_64(x) rte_bswap64(x) >> + >> +#else /* RTE_BIG_ENDIAN */ >> +#error "LoongArch not support big endian!" >> +#endif >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_BYTEORDER_LOONGARCH_H_ */ >> diff --git a/lib/eal/loongarch/include/rte_cpuflags.h b/lib/eal/loongarch/include/rte_cpuflags.h >> new file mode 100644 >> index 0000000000..d9121a00a8 >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_cpuflags.h >> @@ -0,0 +1,39 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_CPUFLAGS_LOONGARCH_H_ >> +#define _RTE_CPUFLAGS_LOONGARCH_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +/** >> + * Enumeration of all CPU features supported >> + */ >> +enum rte_cpu_flag_t { >> + RTE_CPUFLAG_CPUCFG = 0, >> + RTE_CPUFLAG_LAM, >> + RTE_CPUFLAG_UAL, >> + RTE_CPUFLAG_FPU, >> + RTE_CPUFLAG_LSX, >> + RTE_CPUFLAG_LASX, >> + RTE_CPUFLAG_CRC32, >> + RTE_CPUFLAG_COMPLEX, >> + RTE_CPUFLAG_CRYPTO, >> + RTE_CPUFLAG_LVZ, >> + RTE_CPUFLAG_LBT_X86, >> + RTE_CPUFLAG_LBT_ARM, >> + RTE_CPUFLAG_LBT_MIPS, >> + /* The last item */ >> + RTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */ >> +}; >> + >> +#include "generic/rte_cpuflags.h" >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_CPUFLAGS_LOONGARCH_H_ */ >> diff --git a/lib/eal/loongarch/include/rte_cycles.h b/lib/eal/loongarch/include/rte_cycles.h >> new file mode 100644 >> index 0000000000..0f1539be1b >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_cycles.h >> @@ -0,0 +1,47 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_CYCLES_LOONGARCH_H_ >> +#define _RTE_CYCLES_LOONGARCH_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include "generic/rte_cycles.h" >> + >> +/** >> + * Read the time base register. >> + * >> + * @return >> + * The time base for this lcore. >> + */ >> +static inline uint64_t >> +rte_rdtsc(void) >> +{ >> + uint64_t count; >> + >> + __asm__ __volatile__ ( >> + "rdtime.d %[cycles], $zero\n" >> + : [cycles] "=r" (count) >> + :: >> + ); >> + return count; >> +} >> + >> +static inline uint64_t >> +rte_rdtsc_precise(void) >> +{ >> + rte_mb(); >> + return rte_rdtsc(); >> +} >> + >> +static inline uint64_t >> +rte_get_tsc_cycles(void) { return rte_rdtsc(); } >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_CYCLES_LOONGARCH_H_ */ >> diff --git a/lib/eal/loongarch/include/rte_io.h b/lib/eal/loongarch/include/rte_io.h >> new file mode 100644 >> index 0000000000..af152a727a >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_io.h >> @@ -0,0 +1,18 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_IO_LOONGARCH_H_ >> +#define _RTE_IO_LOONGARCH_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include "generic/rte_io.h" >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_IO_LOONGARCH_H_ */ >> diff --git a/lib/eal/loongarch/include/rte_memcpy.h b/lib/eal/loongarch/include/rte_memcpy.h >> new file mode 100644 >> index 0000000000..e7b91e9ce4 >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_memcpy.h >> @@ -0,0 +1,61 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_MEMCPY_LOONGARCH_H_ >> +#define _RTE_MEMCPY_LOONGARCH_H_ >> + >> +#include <stdint.h> >> +#include <string.h> >> + >> +#include "rte_common.h" >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include "generic/rte_memcpy.h" >> + >> +static inline void >> +rte_mov16(uint8_t *dst, const uint8_t *src) >> +{ >> + memcpy(dst, src, 16); >> +} >> + >> +static inline void >> +rte_mov32(uint8_t *dst, const uint8_t *src) >> +{ >> + memcpy(dst, src, 32); >> +} >> + >> +static inline void >> +rte_mov48(uint8_t *dst, const uint8_t *src) >> +{ >> + memcpy(dst, src, 48); >> +} >> + >> +static inline void >> +rte_mov64(uint8_t *dst, const uint8_t *src) >> +{ >> + memcpy(dst, src, 64); >> +} >> + >> +static inline void >> +rte_mov128(uint8_t *dst, const uint8_t *src) >> +{ >> + memcpy(dst, src, 128); >> +} >> + >> +static inline void >> +rte_mov256(uint8_t *dst, const uint8_t *src) >> +{ >> + memcpy(dst, src, 256); >> +} >> + >> +#define rte_memcpy(d, s, n) memcpy((d), (s), (n)) >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_MEMCPY_LOONGARCH_H_ */ >> diff --git a/lib/eal/loongarch/include/rte_pause.h b/lib/eal/loongarch/include/rte_pause.h >> new file mode 100644 >> index 0000000000..438de23128 >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_pause.h >> @@ -0,0 +1,24 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_PAUSE_LOONGARCH_H_ >> +#define _RTE_PAUSE_LOONGARCH_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include "rte_atomic.h" >> + >> +#include "generic/rte_pause.h" >> + >> +static inline void rte_pause(void) >> +{ >> +} >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_PAUSE_LOONGARCH_H_ */ >> diff --git a/lib/eal/loongarch/include/rte_power_intrinsics.h b/lib/eal/loongarch/include/rte_power_intrinsics.h >> new file mode 100644 >> index 0000000000..b6a2c0d82e >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_power_intrinsics.h >> @@ -0,0 +1,20 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_POWER_INTRINSIC_LOONGARCH_H_ >> +#define _RTE_POWER_INTRINSIC_LOONGARCH_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include <rte_common.h> >> + >> +#include "generic/rte_power_intrinsics.h" >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_POWER_INTRINSIC_LOONGARCH_H_ */ >> diff --git a/lib/eal/loongarch/include/rte_prefetch.h b/lib/eal/loongarch/include/rte_prefetch.h >> new file mode 100644 >> index 0000000000..0fd9262ea8 >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_prefetch.h >> @@ -0,0 +1,47 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_PREFETCH_LOONGARCH_H_ >> +#define _RTE_PREFETCH_LOONGARCH_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include <rte_common.h> >> +#include "generic/rte_prefetch.h" >> + >> +static inline void rte_prefetch0(const volatile void *p) >> +{ >> + __builtin_prefetch((const void *)(uintptr_t)p, 0, 3); >> +} >> + >> +static inline void rte_prefetch1(const volatile void *p) >> +{ >> + __builtin_prefetch((const void *)(uintptr_t)p, 0, 2); >> +} >> + >> +static inline void rte_prefetch2(const volatile void *p) >> +{ >> + __builtin_prefetch((const void *)(uintptr_t)p, 0, 1); >> +} >> + >> +static inline void rte_prefetch_non_temporal(const volatile void *p) >> +{ >> + /* non-temporal version not available, fallback to rte_prefetch0 */ >> + rte_prefetch0(p); >> +} >> + >> +__rte_experimental >> +static inline void >> +rte_cldemote(const volatile void *p) >> +{ >> + RTE_SET_USED(p); >> +} >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_PREFETCH_LOONGARCH_H_ */ >> diff --git a/lib/eal/loongarch/include/rte_rwlock.h b/lib/eal/loongarch/include/rte_rwlock.h >> new file mode 100644 >> index 0000000000..aac6f60120 >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_rwlock.h >> @@ -0,0 +1,42 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_RWLOCK_LOONGARCH_H_ >> +#define _RTE_RWLOCK_LOONGARCH_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include "generic/rte_rwlock.h" >> + >> +static inline void >> +rte_rwlock_read_lock_tm(rte_rwlock_t *rwl) >> +{ >> + rte_rwlock_read_lock(rwl); >> +} >> + >> +static inline void >> +rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl) >> +{ >> + rte_rwlock_read_unlock(rwl); >> +} >> + >> +static inline void >> +rte_rwlock_write_lock_tm(rte_rwlock_t *rwl) >> +{ >> + rte_rwlock_write_lock(rwl); >> +} >> + >> +static inline void >> +rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl) >> +{ >> + rte_rwlock_write_unlock(rwl); >> +} >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_RWLOCK_LOONGARCH_H_ */ >> diff --git a/lib/eal/loongarch/include/rte_spinlock.h b/lib/eal/loongarch/include/rte_spinlock.h >> new file mode 100644 >> index 0000000000..dd07538c7f >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_spinlock.h >> @@ -0,0 +1,64 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_SPINLOCK_LOONGARCH_H_ >> +#define _RTE_SPINLOCK_LOONGARCH_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include <rte_common.h> >> +#include "generic/rte_spinlock.h" >> + >> +#ifndef RTE_FORCE_INTRINSICS >> +# error Platform must be built with RTE_FORCE_INTRINSICS >> +#endif >> + >> +static inline int rte_tm_supported(void) >> +{ >> + return 0; >> +} >> + >> +static inline void >> +rte_spinlock_lock_tm(rte_spinlock_t *sl) >> +{ >> + rte_spinlock_lock(sl); /* fall-back */ >> +} >> + >> +static inline int >> +rte_spinlock_trylock_tm(rte_spinlock_t *sl) >> +{ >> + return rte_spinlock_trylock(sl); >> +} >> + >> +static inline void >> +rte_spinlock_unlock_tm(rte_spinlock_t *sl) >> +{ >> + rte_spinlock_unlock(sl); >> +} >> + >> +static inline void >> +rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr) >> +{ >> + rte_spinlock_recursive_lock(slr); /* fall-back */ >> +} >> + >> +static inline void >> +rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr) >> +{ >> + rte_spinlock_recursive_unlock(slr); >> +} >> + >> +static inline int >> +rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr) >> +{ >> + return rte_spinlock_recursive_trylock(slr); >> +} >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_SPINLOCK_LOONGARCH_H_ */ >> diff --git a/lib/eal/loongarch/include/rte_vect.h b/lib/eal/loongarch/include/rte_vect.h >> new file mode 100644 >> index 0000000000..5951a2674c >> --- /dev/null >> +++ b/lib/eal/loongarch/include/rte_vect.h >> @@ -0,0 +1,65 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#ifndef _RTE_VECT_LOONGARCH_H_ >> +#define _RTE_VECT_LOONGARCH_H_ >> + >> +#include <stdint.h> >> +#include "generic/rte_vect.h" >> +#include "rte_common.h" >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED >> + >> +typedef union xmm { >> + int8_t i8[16]; >> + int16_t i16[8]; >> + int32_t i32[4]; >> + int64_t i64[2]; >> + uint8_t u8[16]; >> + uint16_t u16[8]; >> + uint32_t u32[4]; >> + uint64_t u64[2]; >> + double pd[2]; >> +} __rte_aligned(16) xmm_t; >> + >> +#define XMM_SIZE (sizeof(xmm_t)) >> +#define XMM_MASK (XMM_SIZE - 1) >> + >> +typedef union rte_xmm { >> + xmm_t x; >> + uint8_t u8[XMM_SIZE / sizeof(uint8_t)]; >> + uint16_t u16[XMM_SIZE / sizeof(uint16_t)]; >> + uint32_t u32[XMM_SIZE / sizeof(uint32_t)]; >> + uint64_t u64[XMM_SIZE / sizeof(uint64_t)]; >> + double pd[XMM_SIZE / sizeof(double)]; >> +} __rte_aligned(16) rte_xmm_t; >> + >> +static inline xmm_t >> +vect_load_128(void *p) >> +{ >> + xmm_t ret = *((xmm_t *)p); >> + >> + return ret; >> +} >> + >> +static inline xmm_t >> +vect_and(xmm_t data, xmm_t mask) >> +{ >> + rte_xmm_t ret = {.x = data }; >> + rte_xmm_t m = {.x = mask }; >> + ret.u64[0] &= m.u64[0]; >> + ret.u64[1] &= m.u64[1]; >> + >> + return ret.x; >> +} >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif >> diff --git a/lib/eal/loongarch/meson.build b/lib/eal/loongarch/meson.build >> new file mode 100644 >> index 0000000000..4dcc27babb >> --- /dev/null >> +++ b/lib/eal/loongarch/meson.build >> @@ -0,0 +1,11 @@ >> +# SPDX-License-Identifier: BSD-3-Clause >> +# Copyright(c) 2022 Loongson Technology Corporation Limited >> + >> +subdir('include') >> + >> +sources += files( >> + 'rte_cpuflags.c', >> + 'rte_cycles.c', >> + 'rte_hypervisor.c', >> + 'rte_power_intrinsics.c', >> +) >> diff --git a/lib/eal/loongarch/rte_cpuflags.c b/lib/eal/loongarch/rte_cpuflags.c >> new file mode 100644 >> index 0000000000..0a75ca58d4 >> --- /dev/null >> +++ b/lib/eal/loongarch/rte_cpuflags.c >> @@ -0,0 +1,93 @@ >> +/* >> + * SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#include "rte_cpuflags.h" >> + >> +#include <elf.h> >> +#include <fcntl.h> >> +#include <assert.h> >> +#include <unistd.h> >> +#include <string.h> >> + >> +/* Symbolic values for the entries in the auxiliary table */ >> +#define AT_HWCAP 16 >> + >> +/* software based registers */ >> +enum cpu_register_t { >> + REG_NONE = 0, >> + REG_HWCAP, >> + REG_MAX >> +}; >> + >> +typedef uint32_t hwcap_registers_t[REG_MAX]; >> + >> +struct feature_entry { >> + uint32_t reg; >> + uint32_t bit; >> +#define CPU_FLAG_NAME_MAX_LEN 64 >> + char name[CPU_FLAG_NAME_MAX_LEN]; >> +}; >> + >> +#define FEAT_DEF(name, reg, bit) \ >> + [RTE_CPUFLAG_##name] = {reg, bit, #name}, >> + >> +const struct feature_entry rte_cpu_feature_table[] = { >> + FEAT_DEF(CPUCFG, REG_HWCAP, 0) >> + FEAT_DEF(LAM, REG_HWCAP, 1) >> + FEAT_DEF(UAL, REG_HWCAP, 2) >> + FEAT_DEF(FPU, REG_HWCAP, 3) >> + FEAT_DEF(LSX, REG_HWCAP, 4) >> + FEAT_DEF(LASX, REG_HWCAP, 5) >> + FEAT_DEF(CRC32, REG_HWCAP, 6) >> + FEAT_DEF(COMPLEX, REG_HWCAP, 7) >> + FEAT_DEF(CRYPTO, REG_HWCAP, 8) >> + FEAT_DEF(LVZ, REG_HWCAP, 9) >> + FEAT_DEF(LBT_X86, REG_HWCAP, 10) >> + FEAT_DEF(LBT_ARM, REG_HWCAP, 11) >> + FEAT_DEF(LBT_MIPS, REG_HWCAP, 12) >> +}; >> + >> +/* >> + * Read AUXV software register and get cpu features for LoongArch >> + */ >> +static void >> +rte_cpu_get_features(hwcap_registers_t out) >> +{ >> + out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); >> +} >> + >> +/* >> + * Checks if a particular flag is available on current machine. >> + */ >> +int >> +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) >> +{ >> + const struct feature_entry *feat; >> + hwcap_registers_t regs = {0}; >> + >> + if (feature >= RTE_CPUFLAG_NUMFLAGS) >> + return -ENOENT; >> + >> + feat = &rte_cpu_feature_table[feature]; >> + if (feat->reg == REG_NONE) >> + return -EFAULT; >> + >> + rte_cpu_get_features(regs); >> + return (regs[feat->reg] >> feat->bit) & 1; >> +} >> + >> +const char * >> +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) >> +{ >> + if (feature >= RTE_CPUFLAG_NUMFLAGS) >> + return NULL; >> + return rte_cpu_feature_table[feature].name; >> +} >> + >> +void >> +rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics) >> +{ >> + memset(intrinsics, 0, sizeof(*intrinsics)); >> +} >> diff --git a/lib/eal/loongarch/rte_cycles.c b/lib/eal/loongarch/rte_cycles.c >> new file mode 100644 >> index 0000000000..582601d335 >> --- /dev/null >> +++ b/lib/eal/loongarch/rte_cycles.c >> @@ -0,0 +1,45 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#include "eal_private.h" >> + >> +#define LOONGARCH_CPUCFG4 0x4 >> +#define CPUCFG4_CCFREQ_MASK 0xFFFFFFFF >> +#define CPUCFG4_CCFREQ_SHIFT 0 >> + >> +#define LOONGARCH_CPUCFG5 0x5 >> +#define CPUCFG5_CCMUL_MASK 0xFFFF >> +#define CPUCFG5_CCMUL_SHIFT 0 >> + >> +#define CPUCFG5_CCDIV_MASK 0xFFFF0000 >> +#define CPUCFG5_CCDIV_SHIFT 16 >> + >> +static __rte_noinline uint32_t >> +read_cpucfg(int arg) >> +{ >> + int ret = 0; >> + >> + __asm__ __volatile__ ( >> + "cpucfg %[var], %[index]\n" >> + : [var]"=r"(ret) >> + : [index]"r"(arg) >> + : >> + ); >> + >> + return ret; >> +} >> + >> +uint64_t >> +get_tsc_freq_arch(void) >> +{ >> + uint32_t base_freq, mul_factor, div_factor; >> + >> + base_freq = read_cpucfg(LOONGARCH_CPUCFG4); >> + mul_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCMUL_MASK) >> >> + CPUCFG5_CCMUL_SHIFT; >> + div_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCDIV_MASK) >> >> + CPUCFG5_CCDIV_SHIFT; >> + >> + return base_freq * mul_factor / div_factor; >> +} >> diff --git a/lib/eal/loongarch/rte_hypervisor.c b/lib/eal/loongarch/rte_hypervisor.c >> new file mode 100644 >> index 0000000000..d044906f71 >> --- /dev/null >> +++ b/lib/eal/loongarch/rte_hypervisor.c >> @@ -0,0 +1,11 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#include "rte_hypervisor.h" >> + >> +enum rte_hypervisor >> +rte_hypervisor_get(void) >> +{ >> + return RTE_HYPERVISOR_UNKNOWN; >> +} >> diff --git a/lib/eal/loongarch/rte_power_intrinsics.c b/lib/eal/loongarch/rte_power_intrinsics.c >> new file mode 100644 >> index 0000000000..a8969c260e >> --- /dev/null >> +++ b/lib/eal/loongarch/rte_power_intrinsics.c >> @@ -0,0 +1,53 @@ >> +/* SPDX-License-Identifier: BSD-3-Clause >> + * Copyright(c) 2022 Loongson Technology Corporation Limited >> + */ >> + >> +#include <errno.h> >> + >> +#include "rte_power_intrinsics.h" >> + >> +/** >> + * This function is not supported on LOONGARCH. >> + */ >> +int >> +rte_power_monitor(const struct rte_power_monitor_cond *pmc, >> + const uint64_t tsc_timestamp) >> +{ >> + RTE_SET_USED(pmc); >> + RTE_SET_USED(tsc_timestamp); >> + >> + return -ENOTSUP; >> +} >> + >> +/** >> + * This function is not supported on LOONGARCH. >> + */ >> +int >> +rte_power_pause(const uint64_t tsc_timestamp) >> +{ >> + RTE_SET_USED(tsc_timestamp); >> + >> + return -ENOTSUP; >> +} >> + >> +/** >> + * This function is not supported on LOONGARCH. >> + */ >> +int >> +rte_power_monitor_wakeup(const unsigned int lcore_id) >> +{ >> + RTE_SET_USED(lcore_id); >> + >> + return -ENOTSUP; >> +} >> + >> +int >> +rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[], >> + const uint32_t num, const uint64_t tsc_timestamp) >> +{ >> + RTE_SET_USED(pmc); >> + RTE_SET_USED(num); >> + RTE_SET_USED(tsc_timestamp); >> + >> + return -ENOTSUP; >> +} >> diff --git a/meson.build b/meson.build >> index 7d6643da3a..de718974d4 100644 >> --- a/meson.build >> +++ b/meson.build >> @@ -56,6 +56,8 @@ elif host_machine.cpu_family().startswith('ppc') >> arch_subdir = 'ppc' >> elif host_machine.cpu_family().startswith('riscv') >> arch_subdir = 'riscv' >> +elif host_machine.cpu_family().startswith('loongarch') >> + arch_subdir = 'loongarch' >> endif > Please insert it earlier, between arm and ppc. OK, thanks. I will fix them to keep the alphabetical order. Thanks, -- Min Zhou ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v7 2/7] net/ixgbe: add vector stubs for LoongArch 2022-09-30 8:02 [PATCH v7 0/7] Introduce support for LoongArch architecture Min Zhou 2022-09-30 8:02 ` [PATCH v7 1/7] eal/loongarch: support " Min Zhou @ 2022-09-30 8:02 ` Min Zhou 2022-09-30 8:02 ` [PATCH v7 3/7] net/memif: set memfd syscall ID on LoongArch Min Zhou ` (6 subsequent siblings) 8 siblings, 0 replies; 20+ messages in thread From: Min Zhou @ 2022-09-30 8:02 UTC (permalink / raw) To: thomas, david.marchand, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, zhoumin Cc: dev, maobibo Similar to RISC-V, the current version for LoongArch do not support vector. Re-use vector processing stubs in ixgbe PMD defined for PPC for LoongArch. This enables ixgbe PMD usage in scalar mode on LoongArch. The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the test-pmd application, l2fwd, l3fwd examples. Signed-off-by: Min Zhou <zhoumin@loongson.cn> --- doc/guides/nics/features/ixgbe.ini | 1 + drivers/net/ixgbe/ixgbe_rxtx.c | 7 +++++-- drivers/net/ixgbe/meson.build | 6 ------ 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/doc/guides/nics/features/ixgbe.ini b/doc/guides/nics/features/ixgbe.ini index ab759a6fb3..97c0a6af9e 100644 --- a/doc/guides/nics/features/ixgbe.ini +++ b/doc/guides/nics/features/ixgbe.ini @@ -52,6 +52,7 @@ FreeBSD = Y Linux = Y Windows = Y ARMv8 = Y +LoongArch64 = Y rv64 = Y x86-32 = Y x86-64 = Y diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 009d9b624a..c9d6ca9efe 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -5957,8 +5957,11 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev, return 0; } -/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */ -#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV) +/* Stubs needed for linkage when RTE_ARCH_PPC_64, RTE_ARCH_RISCV or + * RTE_ARCH_LOONGARCH is set. + */ +#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV) || \ + defined(RTE_ARCH_LOONGARCH) int ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev) { diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build index 80ab012448..a18908ef7c 100644 --- a/drivers/net/ixgbe/meson.build +++ b/drivers/net/ixgbe/meson.build @@ -1,12 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -if arch_subdir == 'loongarch' - build = false - reason = 'not supported on LoongArch' - subdir_done() -endif - cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS'] subdir('base') -- 2.31.1 ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v7 3/7] net/memif: set memfd syscall ID on LoongArch 2022-09-30 8:02 [PATCH v7 0/7] Introduce support for LoongArch architecture Min Zhou 2022-09-30 8:02 ` [PATCH v7 1/7] eal/loongarch: support " Min Zhou 2022-09-30 8:02 ` [PATCH v7 2/7] net/ixgbe: add vector stubs for LoongArch Min Zhou @ 2022-09-30 8:02 ` Min Zhou 2022-09-30 8:02 ` [PATCH v7 4/7] net/tap: set BPF syscall ID for LoongArch Min Zhou ` (5 subsequent siblings) 8 siblings, 0 replies; 20+ messages in thread From: Min Zhou @ 2022-09-30 8:02 UTC (permalink / raw) To: thomas, david.marchand, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, zhoumin Cc: dev, maobibo Define the missing __NR_memfd_create syscall id to enable the memif PMD on LoongArch. Signed-off-by: Min Zhou <zhoumin@loongson.cn> --- drivers/net/memif/meson.build | 6 ------ drivers/net/memif/rte_eth_memif.h | 2 ++ 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build index 30c0fbc798..680bc8631c 100644 --- a/drivers/net/memif/meson.build +++ b/drivers/net/memif/meson.build @@ -1,12 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright 2018-2019 Cisco Systems, Inc. All rights reserved. -if arch_subdir == 'loongarch' - build = false - reason = 'not supported on LoongArch' - subdir_done() -endif - if not is_linux build = false reason = 'only supported on Linux' diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h index 81e7dceae0..eb692aee68 100644 --- a/drivers/net/memif/rte_eth_memif.h +++ b/drivers/net/memif/rte_eth_memif.h @@ -182,6 +182,8 @@ const char *memif_version(void); #define __NR_memfd_create 356 #elif defined __riscv #define __NR_memfd_create 279 +#elif defined __loongarch__ +#define __NR_memfd_create 279 #else #error "__NR_memfd_create unknown for this architecture" #endif -- 2.31.1 ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v7 4/7] net/tap: set BPF syscall ID for LoongArch 2022-09-30 8:02 [PATCH v7 0/7] Introduce support for LoongArch architecture Min Zhou ` (2 preceding siblings ...) 2022-09-30 8:02 ` [PATCH v7 3/7] net/memif: set memfd syscall ID on LoongArch Min Zhou @ 2022-09-30 8:02 ` Min Zhou 2022-09-30 8:02 ` [PATCH v7 5/7] examples/l3fwd: enable LoongArch operation Min Zhou ` (4 subsequent siblings) 8 siblings, 0 replies; 20+ messages in thread From: Min Zhou @ 2022-09-30 8:02 UTC (permalink / raw) To: thomas, david.marchand, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, zhoumin Cc: dev, maobibo Define the missing __NR_bpf syscall id to enable the tap PMD on LoongArch. Signed-off-by: Min Zhou <zhoumin@loongson.cn> --- drivers/net/tap/meson.build | 6 ------ drivers/net/tap/tap_bpf.h | 2 ++ 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build index f0d03069cd..c09713a67b 100644 --- a/drivers/net/tap/meson.build +++ b/drivers/net/tap/meson.build @@ -1,12 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright 2018 Luca Boccassi <bluca@debian.org> -if arch_subdir == 'loongarch' - build = false - reason = 'not supported on LoongArch' - subdir_done() -endif - if not is_linux build = false reason = 'only supported on Linux' diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h index 639bdf3a79..0d38bc111f 100644 --- a/drivers/net/tap/tap_bpf.h +++ b/drivers/net/tap/tap_bpf.h @@ -103,6 +103,8 @@ union bpf_attr { # define __NR_bpf 361 # elif defined(__riscv) # define __NR_bpf 280 +# elif defined(__loongarch__) +# define __NR_bpf 280 # else # error __NR_bpf not defined # endif -- 2.31.1 ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v7 5/7] examples/l3fwd: enable LoongArch operation 2022-09-30 8:02 [PATCH v7 0/7] Introduce support for LoongArch architecture Min Zhou ` (3 preceding siblings ...) 2022-09-30 8:02 ` [PATCH v7 4/7] net/tap: set BPF syscall ID for LoongArch Min Zhou @ 2022-09-30 8:02 ` Min Zhou 2022-09-30 8:02 ` [PATCH v7 6/7] test/cpuflags: add test for LoongArch cpu flag Min Zhou ` (3 subsequent siblings) 8 siblings, 0 replies; 20+ messages in thread From: Min Zhou @ 2022-09-30 8:02 UTC (permalink / raw) To: thomas, david.marchand, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, zhoumin Cc: dev, maobibo Add missing em_mask_key() implementation to enable the l3fwd to be run on LoongArch. Signed-off-by: Min Zhou <zhoumin@loongson.cn> --- examples/l3fwd/l3fwd_em.c | 8 ++++++++ examples/l3fwd/meson.build | 6 ------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c index 0531282a1f..a203dc9e46 100644 --- a/examples/l3fwd/l3fwd_em.c +++ b/examples/l3fwd/l3fwd_em.c @@ -247,6 +247,14 @@ em_mask_key(void *key, xmm_t mask) return vect_and(data, mask); } +#elif defined(RTE_ARCH_LOONGARCH) +static inline xmm_t +em_mask_key(void *key, xmm_t mask) +{ + xmm_t data = vect_load_128(key); + + return vect_and(data, mask); +} #else #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain #endif diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build index d2f2d96099..b40244a941 100644 --- a/examples/l3fwd/meson.build +++ b/examples/l3fwd/meson.build @@ -6,12 +6,6 @@ # To build this example as a standalone application with an already-installed # DPDK instance, use 'make' -if arch_subdir == 'loongarch' - build = false - reason = 'not supported on LoongArch' - subdir_done() -endif - allow_experimental_apis = true deps += ['acl', 'hash', 'lpm', 'fib', 'eventdev'] sources = files( -- 2.31.1 ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v7 6/7] test/cpuflags: add test for LoongArch cpu flag 2022-09-30 8:02 [PATCH v7 0/7] Introduce support for LoongArch architecture Min Zhou ` (4 preceding siblings ...) 2022-09-30 8:02 ` [PATCH v7 5/7] examples/l3fwd: enable LoongArch operation Min Zhou @ 2022-09-30 8:02 ` Min Zhou 2022-09-30 8:02 ` [PATCH v7 7/7] ci: add LOONGARCH64 cross compilation job Min Zhou ` (2 subsequent siblings) 8 siblings, 0 replies; 20+ messages in thread From: Min Zhou @ 2022-09-30 8:02 UTC (permalink / raw) To: thomas, david.marchand, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, zhoumin Cc: dev, maobibo Add checks for all flag values defined in the LoongArch cpu feature table. Signed-off-by: Min Zhou <zhoumin@loongson.cn> --- app/test/test_cpuflags.c | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c index 98a99c2c7d..a0e342ae48 100644 --- a/app/test/test_cpuflags.c +++ b/app/test/test_cpuflags.c @@ -281,6 +281,47 @@ test_cpuflags(void) CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z); #endif +#if defined(RTE_ARCH_LOONGARCH) + printf("Check for CPUCFG:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_CPUCFG); + + printf("Check for LAM:\t\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_LAM); + + printf("Check for UAL:\t\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_UAL); + + printf("Check for FPU:\t\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_FPU); + + printf("Check for LSX:\t\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_LSX); + + printf("Check for LASX:\t\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_LASX); + + printf("Check for CRC32:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_CRC32); + + printf("Check for COMPLEX:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_COMPLEX); + + printf("Check for CRYPTO:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_CRYPTO); + + printf("Check for LVZ:\t\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_LVZ); + + printf("Check for LBT_X86:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_LBT_X86); + + printf("Check for LBT_ARM:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_LBT_ARM); + + printf("Check for LBT_MIPS:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_LBT_MIPS); +#endif + /* * Check if invalid data is handled properly */ -- 2.31.1 ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v7 7/7] ci: add LOONGARCH64 cross compilation job 2022-09-30 8:02 [PATCH v7 0/7] Introduce support for LoongArch architecture Min Zhou ` (5 preceding siblings ...) 2022-09-30 8:02 ` [PATCH v7 6/7] test/cpuflags: add test for LoongArch cpu flag Min Zhou @ 2022-09-30 8:02 ` Min Zhou 2022-09-30 8:13 ` [PATCH v7 0/7] Introduce support for LoongArch architecture David Marchand 2022-10-04 6:59 ` David Marchand 8 siblings, 0 replies; 20+ messages in thread From: Min Zhou @ 2022-09-30 8:02 UTC (permalink / raw) To: thomas, david.marchand, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, zhoumin Cc: dev, maobibo Checks cross-compilation using Ubuntu 20.04 x86 for LoongArch. Signed-off-by: Min Zhou <zhoumin@loongson.cn> --- .ci/linux-build.sh | 10 ++++++++++ .github/workflows/build.yml | 10 +++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh index 06104eca22..256cf9c400 100755 --- a/.ci/linux-build.sh +++ b/.ci/linux-build.sh @@ -66,6 +66,16 @@ if [ "$AARCH64" = "true" ]; then fi fi +if [ "$LOONGARCH64" = "true" ]; then + cross_tools_tar="/tmp/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz" + cross_tools_dir="/tmp/loongarch64-cross-tools" + rm -rf $cross_tools_dir + mkdir $cross_tools_dir + tar -xf $cross_tools_tar -C $cross_tools_dir --strip-components 1 + export PATH=$PATH:$cross_tools_dir/bin + cross_file=config/loongarch/loongarch_loongarch64_linux_gcc +fi + if [ "$MINGW" = "true" ]; then cross_file=config/x86/cross-mingw fi diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index bf17d2b278..28c7906ecb 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -22,6 +22,7 @@ jobs: CC: ccache ${{ matrix.config.compiler }} DEF_LIB: ${{ matrix.config.library }} LIBABIGAIL_VERSION: libabigail-1.8 + LOONGARCH64: ${{ matrix.config.cross == 'loongarch64' }} MINGW: ${{ matrix.config.cross == 'mingw' }} MINI: ${{ matrix.config.mini != '' }} PPC64LE: ${{ matrix.config.cross == 'ppc64le' }} @@ -67,6 +68,10 @@ jobs: compiler: gcc library: shared cross: aarch64 + - os: ubuntu-20.04 + compiler: gcc + library: shared + cross: loongarch64 - os: ubuntu-20.04 compiler: gcc library: static @@ -118,7 +123,7 @@ jobs: run: sudo apt install -y ccache libnuma-dev python3-setuptools python3-wheel python3-pip python3-pyelftools ninja-build libbsd-dev libpcap-dev libibverbs-dev libcrypto++-dev libfdt-dev libjansson-dev - libarchive-dev + libarchive-dev wget - name: Install libabigail build dependencies if no cache is available if: env.ABI_CHECKS == 'true' && steps.libabigail-cache.outputs.cache-hit != 'true' run: sudo apt install -y autoconf automake libtool pkg-config libxml2-dev @@ -138,6 +143,9 @@ jobs: - name: Install riscv64 cross compiling packages if: env.RISCV64 == 'true' run: sudo apt install -y crossbuild-essential-riscv64 + - name: Install loongarch64 cross compiling packages + if: env.LOONGARCH64 == 'true' + run: sudo wget -P /tmp/ https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz - name: Install test tools packages if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64 != 'true' || env.RUN_TESTS == 'true' run: sudo apt install -y gdb jq -- 2.31.1 ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v7 0/7] Introduce support for LoongArch architecture 2022-09-30 8:02 [PATCH v7 0/7] Introduce support for LoongArch architecture Min Zhou ` (6 preceding siblings ...) 2022-09-30 8:02 ` [PATCH v7 7/7] ci: add LOONGARCH64 cross compilation job Min Zhou @ 2022-09-30 8:13 ` David Marchand 2022-09-30 10:05 ` zhoumin 2022-10-04 6:59 ` David Marchand 8 siblings, 1 reply; 20+ messages in thread From: David Marchand @ 2022-09-30 8:13 UTC (permalink / raw) To: Min Zhou Cc: thomas, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo Hello, On Fri, Sep 30, 2022 at 10:02 AM Min Zhou <zhoumin@loongson.cn> wrote: > > Dear team, > > The following patch set is intended to support DPDK running on LoongArch > architecture. > > LoongArch is the general processor architecture of Loongson Corporation > and is a new RISC ISA, which is a bit like MIPS or RISC-V. > > The online documents of LoongArch architecture are here: > https://loongson.github.io/LoongArch-Documentation/README-EN.html > > The latest build tools for LoongArch (binary) can be downloaded from: > https://github.com/loongson/build-tools Could you confirm which sources have been used to generate it? and instructions to compile it? > > v7: > - rebase the patchset on the main repository > - add errno.h to rte_power_intrinsics.c according with > commit 72b452c5f259 Thanks, I will look at this last revision. There is still one aspect that is unclear to me. How will the DPDK community make sure changes won't break this architecture? (I mean, runtime checks, not only compilation) IOW, what do you plan to hook to our CI to test patches submitted to the mailing list? -- David Marchand ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v7 0/7] Introduce support for LoongArch architecture 2022-09-30 8:13 ` [PATCH v7 0/7] Introduce support for LoongArch architecture David Marchand @ 2022-09-30 10:05 ` zhoumin 2022-09-30 14:20 ` David Marchand 0 siblings, 1 reply; 20+ messages in thread From: zhoumin @ 2022-09-30 10:05 UTC (permalink / raw) To: David Marchand Cc: thomas, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo Hi, David, Thanks a lot for your kind reply. On Fri, Sep 30, 2022 at 16:13, David Marchand wrote: > Hello, > > On Fri, Sep 30, 2022 at 10:02 AM Min Zhou <zhoumin@loongson.cn> wrote: >> Dear team, >> >> The following patch set is intended to support DPDK running on LoongArch >> architecture. >> >> LoongArch is the general processor architecture of Loongson Corporation >> and is a new RISC ISA, which is a bit like MIPS or RISC-V. >> >> The online documents of LoongArch architecture are here: >> https://loongson.github.io/LoongArch-Documentation/README-EN.html >> >> The latest build tools for LoongArch (binary) can be downloaded from: >> https://github.com/loongson/build-tools > Could you confirm which sources have been used to generate it? and > instructions to compile it? Only the cross compiler [1] is required. The instructions can be found in the new added file cross_build_dpdk_for_loongarch.rst. I had added the CI job for cross compiling DPDK for LoongArch in patch v7 7/7. The CI job can run successfully if without the GCC warning caused by vhost. >> v7: >> - rebase the patchset on the main repository >> - add errno.h to rte_power_intrinsics.c according with >> commit 72b452c5f259 > Thanks, I will look at this last revision. > > > There is still one aspect that is unclear to me. > How will the DPDK community make sure changes won't break this > architecture? (I mean, runtime checks, not only compilation) > IOW, what do you plan to hook to our CI to test patches submitted to > the mailing list? We can send our machine to UNH lab, but it may take a long time. GHA seems to be a good choice. However, I found that the codes of CI runner of GHA [2] are arch-specific. So the CI runner currently cannot run on LoongArch machine. Are there other CI clients which are not arch-specific and can be used for DPDK? We can provide machines accessible by the public network. These machines run Loongnix-server system which was built based on the source rpms of CentOS 8. We can deploy DPDK CI client on these machines. [1] https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz [2] https://github.com/actions/runner -- Thanks, Min Zhou ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v7 0/7] Introduce support for LoongArch architecture 2022-09-30 10:05 ` zhoumin @ 2022-09-30 14:20 ` David Marchand 2022-10-01 14:25 ` zhoumin 2022-10-03 8:14 ` Ali Alnubani 0 siblings, 2 replies; 20+ messages in thread From: David Marchand @ 2022-09-30 14:20 UTC (permalink / raw) To: zhoumin Cc: thomas, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo, Aaron Conole, Ali Alnubani, dpdklab, ci On Fri, Sep 30, 2022 at 12:05 PM zhoumin <zhoumin@loongson.cn> wrote: > On Fri, Sep 30, 2022 at 16:13, David Marchand wrote: > > On Fri, Sep 30, 2022 at 10:02 AM Min Zhou <zhoumin@loongson.cn> wrote: > >> > >> The online documents of LoongArch architecture are here: > >> https://loongson.github.io/LoongArch-Documentation/README-EN.html > >> > >> The latest build tools for LoongArch (binary) can be downloaded from: > >> https://github.com/loongson/build-tools > > Could you confirm which sources have been used to generate it? and > > instructions to compile it? > > Only the cross compiler [1] is required. The instructions can be found in > the new added file cross_build_dpdk_for_loongarch.rst. I had added the > CI job for cross compiling DPDK for LoongArch in patch v7 7/7. The CI job > can run successfully if without the GCC warning caused by vhost. - Sorry, but those instructions are not useful. Is this architecture support in upstream gcc not functional? Maybe I missed the information.. I spent some time at the different links in the docs and in github, but I always end up with a set of headers, or binaries, and no reference to the exact sources that were used. I have limited trust in binaries uploaded somewhere in github. I don't want to spend more time on this. What I ask for, is clear instructions how to get the toolchain sources, and how to generate this toolchain. - About the vhost compilation issue, a fix in the same area of the code is in progress. It will take some time to get the fix. I will postpone merging the last patch until the vhost fix is ready. (I am rather confident all of this will be resolved by the time 22.11 is released). > > >> v7: > >> - rebase the patchset on the main repository > >> - add errno.h to rte_power_intrinsics.c according with > >> commit 72b452c5f259 > > Thanks, I will look at this last revision. > > > > > > There is still one aspect that is unclear to me. > > How will the DPDK community make sure changes won't break this > > architecture? (I mean, runtime checks, not only compilation) > > IOW, what do you plan to hook to our CI to test patches submitted to > > the mailing list? > > We can send our machine to UNH lab, but it may take a long time. > > GHA seems to be a good choice. However, I found that the codes of CI > runner of GHA [2] are arch-specific. So the CI runner currently cannot > run on > LoongArch machine. I see. The better solution is probably to go with "your" own CI so that that LoongArch has runtime non regression (functional and performance) tests. See below. > > Are there other CI clients which are not arch-specific and can be used > for DPDK? > We can provide machines accessible by the public network. These machines run > Loongnix-server system which was built based on the source rpms of CentOS 8. > We can deploy DPDK CI client on these machines. There is no "DPDK CI client" per se. The DPDK project has a distributed CI made of at least 3 CI entities. Those CI test patches and post reports via mail: the ovsrobot, Intel CI and UNH lab. A CI retrieves patches from patchwork, a set of scripts is available in https://git.dpdk.org/tools/dpdk-ci/ (especially the poll-pw script). Then the way the patches are tested is something each CI handles on its side: - the ovsrobot creates a branch per series under the ovsrobot/dpdk github repository, and let GitHub action run (this is how your current series has been tested in GHA), - Intel CI have their own tool for which I have little detail, - UNH lab have their infrastructure too, using some Jenkins iirc. They provide a dashboard for reports https://lab.dpdk.org/results/dashboard/ and to get all details and logs. The common point is that, at the end of testing a series, a test report is sent to the (sender-restricted) test-report@ mailing list. Those reports could be done per patch, but given the amount of patches on the dev@ mailing list, the consensus is to test the whole series and report back against the last patch of a series. All of this is gathered by patchwork (the details of how it is done are not 100% clear to me, maybe Ali can confirm later if a modification is required). If you look at your v7 series, you will see: https://patchwork.dpdk.org/project/dpdk/list/?series=24929&state=%2A&archive=both - ovsrobot: ci/github-robot link http://mails.dpdk.org/archives/test-report/2022-September/310836.html - Intel CI: ci/Intel-* links, for example on the compilation test http://mails.dpdk.org/archives/test-report/2022-September/310822.html - UNH lab: all ci/iol-* links, for example on the compilation test http://mails.dpdk.org/archives/test-report/2022-September/310834.html So what LoongSoon could do is setup some Loongnix systems with a similar infrastructure and provide (native?) compilation and runtime test reports. I Cc'd a few people involved in all this. And there is the ci@ mailing list where all CI people can discuss. -- David Marchand ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v7 0/7] Introduce support for LoongArch architecture 2022-09-30 14:20 ` David Marchand @ 2022-10-01 14:25 ` zhoumin 2022-10-03 16:30 ` David Marchand 2022-10-03 8:14 ` Ali Alnubani 1 sibling, 1 reply; 20+ messages in thread From: zhoumin @ 2022-10-01 14:25 UTC (permalink / raw) To: David Marchand Cc: thomas, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo, Aaron Conole, Ali Alnubani, dpdklab, ci [-- Attachment #1: Type: text/plain, Size: 14977 bytes --] Hi, David, Thanks a lot for your helpful reply. On Fri, Sep 30, 2022 at 22:20, David Marchand wrote: > On Fri, Sep 30, 2022 at 12:05 PM zhoumin<zhoumin@loongson.cn> wrote: >> On Fri, Sep 30, 2022 at 16:13, David Marchand wrote: >>> On Fri, Sep 30, 2022 at 10:02 AM Min Zhou<zhoumin@loongson.cn> wrote: >>>> The online documents of LoongArch architecture are here: >>>> https://loongson.github.io/LoongArch-Documentation/README-EN.html >>>> >>>> The latest build tools for LoongArch (binary) can be downloaded from: >>>> https://github.com/loongson/build-tools >>> Could you confirm which sources have been used to generate it? and >>> instructions to compile it? >> Only the cross compiler [1] is required. The instructions can be found in >> the new added file cross_build_dpdk_for_loongarch.rst. I had added the >> CI job for cross compiling DPDK for LoongArch in patch v7 7/7. The CI job >> can run successfully if without the GCC warning caused by vhost. > - Sorry, but those instructions are not useful. > > Is this architecture support in upstream gcc not functional? > > Maybe I missed the information.. I spent some time at the different > links in the docs and in github, but I always end up with a set of > headers, or binaries, and no reference to the exact sources that were > used. > I have limited trust in binaries uploaded somewhere in github. > I don't want to spend more time on this. > > What I ask for, is clear instructions how to get the toolchain > sources, and how to generate this toolchain. I'm Sorry, I misunderstood the 'instructions' you said. The process of making the toolchain is a little complicated. So I made a script used to generate the toolchain from source codes. The content of the script is as follows: #!/bin/bash # Prepare the working directories export SYSDIR=/tmp/la_cross_tools mkdir -pv ${SYSDIR} mkdir -pv ${SYSDIR}/downloads mkdir -pv ${SYSDIR}/build install -dv ${SYSDIR}/cross-tools install -dv ${SYSDIR}/sysroot set +h umask 022 # Set the environment variables to be used next export BUILDDIR="${SYSDIR}/build" export DOWNLOADDIR="${SYSDIR}/downloads" export LC_ALL=POSIX export CROSS_HOST="$(echo $MACHTYPE | sed "s/$(echo $MACHTYPE | cut -d- -f2)/cross/")" export CROSS_TARGET="loongarch64-unknown-linux-gnu" export MABI="lp64d" export BUILD64="-mabi=lp64d" export PATH=${SYSDIR}/cross-tools/bin:/bin:/usr/bin export JOBS=-j8 unset CFLAGS unset CXXFLAGS # Download the source code archives pushd $DOWNLOADDIR wget https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.19.tar.gz wget https://ftp.gnu.org/gnu/gmp/gmp-6.2.1.tar.xz wget https://www.mpfr.org/mpfr-4.1.0/mpfr-4.1.0.tar.xz wget https://ftp.gnu.org/gnu/mpc/mpc-1.2.1.tar.gz wget https://ftp.gnu.org/gnu/libc/glibc-2.36.tar.xz popd # Make and install the linux header files tar xvf ${DOWNLOADDIR}/linux-5.19.tar.gz -C ${BUILDDIR} pushd ${BUILDDIR}/linux-5.19 make mrproper make ARCH=loongarch INSTALL_HDR_PATH=dest headers_install find dest/include -name '.*' -delete mkdir -pv ${SYSDIR}/sysroot/usr/include cp -rv dest/include/* ${SYSDIR}/sysroot/usr/include popd # Prepare the binutils source code git clone git://sourceware.org/git/binutils-gdb.git --depth 1 pushd binutils-gdb git archive --format=tar.gz --prefix=binutils-2.38/ --output ../binutils-2.38.tar.gz "master" popd mv binutils-2.38.tar.gz ${DOWNLOADDIR} # Make and install the binutils files tar xvf ${DOWNLOADDIR}/binutils-2.38.tar.gz -C ${BUILDDIR} pushd ${BUILDDIR}/binutils-2.38 rm -rf gdb* libdecnumber readline sim mkdir tools-build pushd tools-build CC=gcc AR=ar AS=as \ ../configure --prefix=${SYSDIR}/cross-tools --build=${CROSS_HOST} --host=${CROSS_HOST} \ --target=${CROSS_TARGET} --with-sysroot=${SYSDIR}/sysroot --disable-nls \ --disable-static --disable-werror --enable-64-bit-bfd make configure-host ${JOBS} make ${JOBS} make install-strip cp -v ../include/libiberty.h ${SYSDIR}/sysroot/usr/include popd popd # Make and install the gmp files used by GCC tar xvf ${DOWNLOADDIR}/gmp-6.2.1.tar.xz -C ${BUILDDIR} pushd ${BUILDDIR}/gmp-6.2.1 ./configure --prefix=${SYSDIR}/cross-tools --enable-cxx --disable-static make ${JOBS} make install popd # Make and install the mpfr files used by GCC tar xvf ${DOWNLOADDIR}/mpfr-4.1.0.tar.xz -C ${BUILDDIR} pushd ${BUILDDIR}/mpfr-4.1.0 ./configure --prefix=${SYSDIR}/cross-tools --disable-static --with-gmp=${SYSDIR}/cross-tools make ${JOBS} make install popd # Make and install the mpc files used by GCC tar xvf ${DOWNLOADDIR}/mpc-1.2.1.tar.gz -C ${BUILDDIR} pushd ${BUILDDIR}/mpc-1.2.1 ./configure --prefix=${SYSDIR}/cross-tools --disable-static --with-gmp=${SYSDIR}/cross-tools make ${JOBS} make install popd # Prepare the gcc source code git clone git://sourceware.org/git/gcc.git --depth 1 pushd gcc git archive --format=tar.gz --prefix=gcc-13.0.0/ --output ../gcc-13.0.0.tar.gz "master" popd mv gcc-13.0.0.tar.gz ${DOWNLOADDIR} # Make and install the simplified GCC files tar xvf ${DOWNLOADDIR}/gcc-13.0.0.tar.gz -C ${BUILDDIR} pushd ${BUILDDIR}/gcc-13.0.0 mkdir tools-build pushd tools-build AR=ar LDFLAGS="-Wl,-rpath,${SYSDIR}/cross-tools/lib" \ ../configure --prefix=${SYSDIR}/cross-tools --build=${CROSS_HOST} --host=${CROSS_HOST} \ --target=${CROSS_TARGET} --disable-nls \ --with-mpfr=${SYSDIR}/cross-tools --with-gmp=${SYSDIR}/cross-tools \ --with-mpc=${SYSDIR}/cross-tools \ --with-newlib --disable-shared --with-sysroot=${SYSDIR}/sysroot \ --disable-decimal-float --disable-libgomp --disable-libitm \ --disable-libsanitizer --disable-libquadmath --disable-threads \ --disable-target-zlib --with-system-zlib --enable-checking=release \ --enable-default-pie \ --enable-languages=c make all-gcc all-target-libgcc ${JOBS} make install-strip-gcc install-strip-target-libgcc popd popd # Make and install the glibc files tar xvf ${DOWNLOADDIR}/glibc-2.36.tar.xz -C ${BUILDDIR} pushd ${BUILDDIR}/glibc-2.36 sed -i "s@5.15.0@4.15.0@g" sysdeps/unix/sysv/linux/loongarch/configure{,.ac} mkdir -v build-64 pushd build-64 BUILD_CC="gcc" CC="${CROSS_TARGET}-gcc ${BUILD64}" \ CXX="${CROSS_TARGET}-gcc ${BUILD64}" \ AR="${CROSS_TARGET}-ar" RANLIB="${CROSS_TARGET}-ranlib" \ ../configure --prefix=/usr --host=${CROSS_TARGET} --build=${CROSS_HOST} \ --libdir=/usr/lib64 --libexecdir=/usr/lib64/glibc \ --with-binutils=${SYSDIR}/cross-tools/bin \ --with-headers=${SYSDIR}/sysroot/usr/include \ --enable-stack-protector=strong --enable-add-ons \ --disable-werror libc_cv_slibdir=/usr/lib64 \ --enable-kernel=4.15 make ${JOBS} make DESTDIR=${SYSDIR}/sysroot install cp -v ../nscd/nscd.conf ${SYSDIR}/sysroot/etc/nscd.conf mkdir -pv ${SYSDIR}/sysroot/var/cache/nscd install -v -Dm644 ../nscd/nscd.tmpfiles \ ${SYSDIR}/sysroot/usr/lib/tmpfiles.d/nscd.conf install -v -Dm644 ../nscd/nscd.service \ ${SYSDIR}/sysroot/usr/lib/systemd/system/nscd.service popd mkdir -v build-locale pushd build-locale ../configure --prefix=/usr --libdir=/usr/lib64 --libexecdir=/usr/lib64/glibc \ --enable-stack-protector=strong --enable-add-ons \ --disable-werror libc_cv_slibdir=/usr/lib64 make ${JOBS} make DESTDIR=${SYSDIR}/sysroot localedata/install-locales popd popd # Make and install the complete GCC files tar xvf ${DOWNLOADDIR}/gcc-13.0.0.tar.gz -C ${BUILDDIR} pushd ${BUILDDIR}/gcc-13.0.0 mkdir tools-build-all pushd tools-build-all AR=ar LDFLAGS="-Wl,-rpath,${SYSDIR}/cross-tools/lib" \ ../configure --prefix=${SYSDIR}/cross-tools --build=${CROSS_HOST} \ --host=${CROSS_HOST} --target=${CROSS_TARGET} \ --with-sysroot=${SYSDIR}/sysroot --with-mpfr=${SYSDIR}/cross-tools \ --with-gmp=${SYSDIR}/cross-tools --with-mpc=${SYSDIR}/cross-tools \ --enable-__cxa_atexit --enable-threads=posix --with-system-zlib \ --enable-libstdcxx-time --enable-checking=release \ --enable-default-pie \ --enable-languages=c,c++,fortran,objc,obj-c++,lto make ${JOBS} make install-strip popd popd I have tested the script on an x86 machine running CentOS 8 system. I successfully used the toolchain generated by this script to cross compiling DPDK for LoongArch. This script may take one hour to complete, which depends on the speed of network and the performance of machine used. This script requires at least 15G of disk space when running. > - About the vhost compilation issue, a fix in the same area of the > code is in progress. > It will take some time to get the fix. > I will postpone merging the last patch until the vhost fix is ready. > (I am rather confident all of this will be resolved by the time 22.11 > is released). Thank you for your concern and efforts on this issue. >>>> v7: >>>> - rebase the patchset on the main repository >>>> - add errno.h to rte_power_intrinsics.c according with >>>> commit 72b452c5f259 >>> Thanks, I will look at this last revision. >>> >>> >>> There is still one aspect that is unclear to me. >>> How will the DPDK community make sure changes won't break this >>> architecture? (I mean, runtime checks, not only compilation) >>> IOW, what do you plan to hook to our CI to test patches submitted to >>> the mailing list? >> We can send our machine to UNH lab, but it may take a long time. >> >> GHA seems to be a good choice. However, I found that the codes of CI >> runner of GHA [2] are arch-specific. So the CI runner currently cannot >> run on >> LoongArch machine. > I see. > > The better solution is probably to go with "your" own CI so that that > LoongArch has runtime non regression (functional and performance) > tests. > See below. Yes, we had spent some time building our own CI system and made the CI system working internally. Our CI system based on Jenkins and DTS. Every time we submit patch to our internal DPDK repository, the Jenkins will be triggered to call DTS for testing the patch. But we have only run less than 100 unit tests currently. More test cases will be added later. >> Are there other CI clients which are not arch-specific and can be used >> for DPDK? >> We can provide machines accessible by the public network. These machines run >> Loongnix-server system which was built based on the source rpms of CentOS 8. >> We can deploy DPDK CI client on these machines. > There is no "DPDK CI client" per se. > > The DPDK project has a distributed CI made of at least 3 CI entities. > > Those CI test patches and post reports via mail: the ovsrobot, Intel > CI and UNH lab. > A CI retrieves patches from patchwork, a set of scripts is available > inhttps://git.dpdk.org/tools/dpdk-ci/ (especially the poll-pw > script). This information is really very useful. Please forgive me for not taking the time to study dpdk-ci. It sounds that dpdk-ci can help us to test patches submitted to the mailing list for LoongArch. > Then the way the patches are tested is something each CI handles on its side: > - the ovsrobot creates a branch per series under the ovsrobot/dpdk > github repository, and let GitHub action run (this is how your current > series has been tested in GHA), > - Intel CI have their own tool for which I have little detail, > - UNH lab have their infrastructure too, using some Jenkins iirc. They > provide a dashboard for reports > https://lab.dpdk.org/results/dashboard/ and to get all details and > logs. > > The common point is that, at the end of testing a series, a test > report is sent to the (sender-restricted) test-report@ mailing list. This process doesn't seem very complicated. We can build a CI system to retrieve patches from patchwork by dpdk-ci and compile, test them on Loongnix system. After completing those jobs, we will generate the test report and send it to the test-report@ mailing list. But my concern is which set of test cases we need to run. Besides, can patchwork gather the test reports we sent and show them on the patch details web page? > Those reports could be done per patch, but given the amount of patches > on the dev@ mailing list, the consensus is to test the whole series > and report back against the last patch of a series. > > All of this is gathered by patchwork (the details of how it is done > are not 100% clear to me, maybe Ali can confirm later if a > modification is required). Thank you for your consideration. > If you look at your v7 series, you will see: > https://patchwork.dpdk.org/project/dpdk/list/?series=24929&state=%2A&archive=both > - ovsrobot: ci/github-robot link > http://mails.dpdk.org/archives/test-report/2022-September/310836.html > - Intel CI: ci/Intel-* links, for example on the compilation test > http://mails.dpdk.org/archives/test-report/2022-September/310822.html > - UNH lab: all ci/iol-* links, for example on the compilation test > http://mails.dpdk.org/archives/test-report/2022-September/310834.html > > So what LoongSoon could do is setup some Loongnix systems with a > similar infrastructure and provide (native?) compilation and runtime > test reports. Yes, we will build the CI system talked above on Loongnix systems to provide compilation and runtime test reports for DPDK on LoongArch machine. But It will take some time to set up this system and make it run stably. We will get this done as soon as possible. > I Cc'd a few people involved in all this. > And there is the ci@ mailing list where all CI people can discuss. Thanks a lot for all your help. -- Thanks, Min Zhou [-- Attachment #2: Type: text/html, Size: 20610 bytes --] ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v7 0/7] Introduce support for LoongArch architecture 2022-10-01 14:25 ` zhoumin @ 2022-10-03 16:30 ` David Marchand 2022-10-04 8:49 ` zhoumin 0 siblings, 1 reply; 20+ messages in thread From: David Marchand @ 2022-10-03 16:30 UTC (permalink / raw) To: zhoumin Cc: thomas, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo, Aaron Conole, Ali Alnubani, dpdklab, ci Hello Min, On Sat, Oct 1, 2022 at 4:26 PM zhoumin <zhoumin@loongson.cn> wrote: > I'm Sorry, I misunderstood the 'instructions' you said. The process of > making the toolchain is a little complicated. So I made a script used to > generate the toolchain from source codes. The content of the script is > as follows: > I successfully generated a cross compilation toolchain with this script. I ran this script in a UBI8 image (iow RHEL8), with the codeready-builder-for-rhel-8-x86_64-rpms repo enabled and the following packages installed: # subscription-manager repos --enable codeready-builder-for-rhel-8-x86_64-rpms # dnf install bison diffutils file flex gcc gcc-c++ git gmp-devel libtool make python3 rsync texinfo wget xz zlib-devel The script below works, but it is really better to run it with -e. # bash -e $script > #!/bin/bash > > # Prepare the working directories > export SYSDIR=/tmp/la_cross_tools > mkdir -pv ${SYSDIR} > mkdir -pv ${SYSDIR}/downloads > mkdir -pv ${SYSDIR}/build > install -dv ${SYSDIR}/cross-tools > install -dv ${SYSDIR}/sysroot > > set +h > umask 022 > # Set the environment variables to be used next > export BUILDDIR="${SYSDIR}/build" > export DOWNLOADDIR="${SYSDIR}/downloads" > export LC_ALL=POSIX > export CROSS_HOST="$(echo $MACHTYPE | sed "s/$(echo $MACHTYPE | cut -d- -f2)/cross/")" > export CROSS_TARGET="loongarch64-unknown-linux-gnu" > export MABI="lp64d" > export BUILD64="-mabi=lp64d" > export PATH=${SYSDIR}/cross-tools/bin:/bin:/usr/bin > export JOBS=-j8 > unset CFLAGS > unset CXXFLAGS > > # Download the source code archives > pushd $DOWNLOADDIR > wget https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.19.tar.gz > wget https://ftp.gnu.org/gnu/gmp/gmp-6.2.1.tar.xz > wget https://www.mpfr.org/mpfr-4.1.0/mpfr-4.1.0.tar.xz > wget https://ftp.gnu.org/gnu/mpc/mpc-1.2.1.tar.gz > wget https://ftp.gnu.org/gnu/libc/glibc-2.36.tar.xz > popd > > # Make and install the linux header files > tar xvf ${DOWNLOADDIR}/linux-5.19.tar.gz -C ${BUILDDIR} > pushd ${BUILDDIR}/linux-5.19 > make mrproper > make ARCH=loongarch INSTALL_HDR_PATH=dest headers_install > find dest/include -name '.*' -delete > mkdir -pv ${SYSDIR}/sysroot/usr/include > cp -rv dest/include/* ${SYSDIR}/sysroot/usr/include > popd > > # Prepare the binutils source code > git clone git://sourceware.org/git/binutils-gdb.git --depth 1 > pushd binutils-gdb > git archive --format=tar.gz --prefix=binutils-2.38/ --output ../binutils-2.38.tar.gz "master" > popd > mv binutils-2.38.tar.gz ${DOWNLOADDIR} > > # Make and install the binutils files > tar xvf ${DOWNLOADDIR}/binutils-2.38.tar.gz -C ${BUILDDIR} > pushd ${BUILDDIR}/binutils-2.38 > rm -rf gdb* libdecnumber readline sim > mkdir tools-build > pushd tools-build > CC=gcc AR=ar AS=as \ > ../configure --prefix=${SYSDIR}/cross-tools --build=${CROSS_HOST} --host=${CROSS_HOST} \ > --target=${CROSS_TARGET} --with-sysroot=${SYSDIR}/sysroot --disable-nls \ > --disable-static --disable-werror --enable-64-bit-bfd > make configure-host ${JOBS} > make ${JOBS} > make install-strip > cp -v ../include/libiberty.h ${SYSDIR}/sysroot/usr/include > popd > popd > > # Make and install the gmp files used by GCC > tar xvf ${DOWNLOADDIR}/gmp-6.2.1.tar.xz -C ${BUILDDIR} > pushd ${BUILDDIR}/gmp-6.2.1 > ./configure --prefix=${SYSDIR}/cross-tools --enable-cxx --disable-static > make ${JOBS} > make install > popd > > # Make and install the mpfr files used by GCC > tar xvf ${DOWNLOADDIR}/mpfr-4.1.0.tar.xz -C ${BUILDDIR} > pushd ${BUILDDIR}/mpfr-4.1.0 > ./configure --prefix=${SYSDIR}/cross-tools --disable-static --with-gmp=${SYSDIR}/cross-tools > make ${JOBS} > make install > popd > > # Make and install the mpc files used by GCC > tar xvf ${DOWNLOADDIR}/mpc-1.2.1.tar.gz -C ${BUILDDIR} > pushd ${BUILDDIR}/mpc-1.2.1 > ./configure --prefix=${SYSDIR}/cross-tools --disable-static --with-gmp=${SYSDIR}/cross-tools > make ${JOBS} > make install > popd > > # Prepare the gcc source code > git clone git://sourceware.org/git/gcc.git --depth 1 > pushd gcc > git archive --format=tar.gz --prefix=gcc-13.0.0/ --output ../gcc-13.0.0.tar.gz "master" > popd > mv gcc-13.0.0.tar.gz ${DOWNLOADDIR} > > # Make and install the simplified GCC files > tar xvf ${DOWNLOADDIR}/gcc-13.0.0.tar.gz -C ${BUILDDIR} > pushd ${BUILDDIR}/gcc-13.0.0 > mkdir tools-build > pushd tools-build > AR=ar LDFLAGS="-Wl,-rpath,${SYSDIR}/cross-tools/lib" \ > ../configure --prefix=${SYSDIR}/cross-tools --build=${CROSS_HOST} --host=${CROSS_HOST} \ > --target=${CROSS_TARGET} --disable-nls \ > --with-mpfr=${SYSDIR}/cross-tools --with-gmp=${SYSDIR}/cross-tools \ > --with-mpc=${SYSDIR}/cross-tools \ > --with-newlib --disable-shared --with-sysroot=${SYSDIR}/sysroot \ > --disable-decimal-float --disable-libgomp --disable-libitm \ > --disable-libsanitizer --disable-libquadmath --disable-threads \ > --disable-target-zlib --with-system-zlib --enable-checking=release \ > --enable-default-pie \ > --enable-languages=c > make all-gcc all-target-libgcc ${JOBS} > make install-strip-gcc install-strip-target-libgcc > popd > popd > > # Make and install the glibc files > tar xvf ${DOWNLOADDIR}/glibc-2.36.tar.xz -C ${BUILDDIR} > pushd ${BUILDDIR}/glibc-2.36 > sed -i "s@5.15.0@4.15.0@g" sysdeps/unix/sysv/linux/loongarch/configure{,.ac} > mkdir -v build-64 > pushd build-64 > BUILD_CC="gcc" CC="${CROSS_TARGET}-gcc ${BUILD64}" \ > CXX="${CROSS_TARGET}-gcc ${BUILD64}" \ > AR="${CROSS_TARGET}-ar" RANLIB="${CROSS_TARGET}-ranlib" \ > ../configure --prefix=/usr --host=${CROSS_TARGET} --build=${CROSS_HOST} \ > --libdir=/usr/lib64 --libexecdir=/usr/lib64/glibc \ > --with-binutils=${SYSDIR}/cross-tools/bin \ > --with-headers=${SYSDIR}/sysroot/usr/include \ > --enable-stack-protector=strong --enable-add-ons \ > --disable-werror libc_cv_slibdir=/usr/lib64 \ > --enable-kernel=4.15 > make ${JOBS} > make DESTDIR=${SYSDIR}/sysroot install > cp -v ../nscd/nscd.conf ${SYSDIR}/sysroot/etc/nscd.conf > mkdir -pv ${SYSDIR}/sysroot/var/cache/nscd > install -v -Dm644 ../nscd/nscd.tmpfiles \ > ${SYSDIR}/sysroot/usr/lib/tmpfiles.d/nscd.conf > install -v -Dm644 ../nscd/nscd.service \ > ${SYSDIR}/sysroot/usr/lib/systemd/system/nscd.service > popd > mkdir -v build-locale > pushd build-locale > ../configure --prefix=/usr --libdir=/usr/lib64 --libexecdir=/usr/lib64/glibc \ > --enable-stack-protector=strong --enable-add-ons \ > --disable-werror libc_cv_slibdir=/usr/lib64 > make ${JOBS} > make DESTDIR=${SYSDIR}/sysroot localedata/install-locales > popd > popd > > # Make and install the complete GCC files > tar xvf ${DOWNLOADDIR}/gcc-13.0.0.tar.gz -C ${BUILDDIR} > pushd ${BUILDDIR}/gcc-13.0.0 > mkdir tools-build-all > pushd tools-build-all > AR=ar LDFLAGS="-Wl,-rpath,${SYSDIR}/cross-tools/lib" \ > ../configure --prefix=${SYSDIR}/cross-tools --build=${CROSS_HOST} \ > --host=${CROSS_HOST} --target=${CROSS_TARGET} \ > --with-sysroot=${SYSDIR}/sysroot --with-mpfr=${SYSDIR}/cross-tools \ > --with-gmp=${SYSDIR}/cross-tools --with-mpc=${SYSDIR}/cross-tools \ > --enable-__cxa_atexit --enable-threads=posix --with-system-zlib \ > --enable-libstdcxx-time --enable-checking=release \ > --enable-default-pie \ > --enable-languages=c,c++,fortran,objc,obj-c++,lto > make ${JOBS} > make install-strip > popd > popd > -- David Marchand ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v7 0/7] Introduce support for LoongArch architecture 2022-10-03 16:30 ` David Marchand @ 2022-10-04 8:49 ` zhoumin 0 siblings, 0 replies; 20+ messages in thread From: zhoumin @ 2022-10-04 8:49 UTC (permalink / raw) To: David Marchand Cc: thomas, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo, Aaron Conole, Ali Alnubani, dpdklab, ci Hi, David, Thanks for your kind reply. On Tue, Oct 4, 2022 at 00:30, David Marchand wrote: > Hello Min, > > On Sat, Oct 1, 2022 at 4:26 PM zhoumin <zhoumin@loongson.cn> wrote: >> I'm Sorry, I misunderstood the 'instructions' you said. The process of >> making the toolchain is a little complicated. So I made a script used to >> generate the toolchain from source codes. The content of the script is >> as follows: >> > I successfully generated a cross compilation toolchain with this script. > > I ran this script in a UBI8 image (iow RHEL8), with the > codeready-builder-for-rhel-8-x86_64-rpms repo enabled and the > following packages installed: > # subscription-manager repos --enable codeready-builder-for-rhel-8-x86_64-rpms > # dnf install bison diffutils file flex gcc gcc-c++ git gmp-devel > libtool make python3 rsync texinfo wget xz zlib-devel I'm sorry. I forgot to give the dependencies for build the cross compilation toolchain. These dependencies can be added into the documentation for LoongArch. Thanks a lot. > The script below works, but it is really better to run it with -e. > > # bash -e $script Yes, thanks. The script will run for a long time. It is better to run it with -e in order to exit quickly when an error has occured. > >> #!/bin/bash >> >> # Prepare the working directories >> export SYSDIR=/tmp/la_cross_tools >> mkdir -pv ${SYSDIR} >> mkdir -pv ${SYSDIR}/downloads >> mkdir -pv ${SYSDIR}/build >> install -dv ${SYSDIR}/cross-tools >> install -dv ${SYSDIR}/sysroot >> >> set +h >> umask 022 >> # Set the environment variables to be used next >> export BUILDDIR="${SYSDIR}/build" >> export DOWNLOADDIR="${SYSDIR}/downloads" >> export LC_ALL=POSIX >> export CROSS_HOST="$(echo $MACHTYPE | sed "s/$(echo $MACHTYPE | cut -d- -f2)/cross/")" >> export CROSS_TARGET="loongarch64-unknown-linux-gnu" >> export MABI="lp64d" >> export BUILD64="-mabi=lp64d" >> export PATH=${SYSDIR}/cross-tools/bin:/bin:/usr/bin >> export JOBS=-j8 >> unset CFLAGS >> unset CXXFLAGS >> >> # Download the source code archives >> pushd $DOWNLOADDIR >> wget https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.19.tar.gz >> wget https://ftp.gnu.org/gnu/gmp/gmp-6.2.1.tar.xz >> wget https://www.mpfr.org/mpfr-4.1.0/mpfr-4.1.0.tar.xz >> wget https://ftp.gnu.org/gnu/mpc/mpc-1.2.1.tar.gz >> wget https://ftp.gnu.org/gnu/libc/glibc-2.36.tar.xz >> popd >> >> # Make and install the linux header files >> tar xvf ${DOWNLOADDIR}/linux-5.19.tar.gz -C ${BUILDDIR} >> pushd ${BUILDDIR}/linux-5.19 >> make mrproper >> make ARCH=loongarch INSTALL_HDR_PATH=dest headers_install >> find dest/include -name '.*' -delete >> mkdir -pv ${SYSDIR}/sysroot/usr/include >> cp -rv dest/include/* ${SYSDIR}/sysroot/usr/include >> popd >> >> # Prepare the binutils source code >> git clone git://sourceware.org/git/binutils-gdb.git --depth 1 >> pushd binutils-gdb >> git archive --format=tar.gz --prefix=binutils-2.38/ --output ../binutils-2.38.tar.gz "master" >> popd >> mv binutils-2.38.tar.gz ${DOWNLOADDIR} >> >> # Make and install the binutils files >> tar xvf ${DOWNLOADDIR}/binutils-2.38.tar.gz -C ${BUILDDIR} >> pushd ${BUILDDIR}/binutils-2.38 >> rm -rf gdb* libdecnumber readline sim >> mkdir tools-build >> pushd tools-build >> CC=gcc AR=ar AS=as \ >> ../configure --prefix=${SYSDIR}/cross-tools --build=${CROSS_HOST} --host=${CROSS_HOST} \ >> --target=${CROSS_TARGET} --with-sysroot=${SYSDIR}/sysroot --disable-nls \ >> --disable-static --disable-werror --enable-64-bit-bfd >> make configure-host ${JOBS} >> make ${JOBS} >> make install-strip >> cp -v ../include/libiberty.h ${SYSDIR}/sysroot/usr/include >> popd >> popd >> >> # Make and install the gmp files used by GCC >> tar xvf ${DOWNLOADDIR}/gmp-6.2.1.tar.xz -C ${BUILDDIR} >> pushd ${BUILDDIR}/gmp-6.2.1 >> ./configure --prefix=${SYSDIR}/cross-tools --enable-cxx --disable-static >> make ${JOBS} >> make install >> popd >> >> # Make and install the mpfr files used by GCC >> tar xvf ${DOWNLOADDIR}/mpfr-4.1.0.tar.xz -C ${BUILDDIR} >> pushd ${BUILDDIR}/mpfr-4.1.0 >> ./configure --prefix=${SYSDIR}/cross-tools --disable-static --with-gmp=${SYSDIR}/cross-tools >> make ${JOBS} >> make install >> popd >> >> # Make and install the mpc files used by GCC >> tar xvf ${DOWNLOADDIR}/mpc-1.2.1.tar.gz -C ${BUILDDIR} >> pushd ${BUILDDIR}/mpc-1.2.1 >> ./configure --prefix=${SYSDIR}/cross-tools --disable-static --with-gmp=${SYSDIR}/cross-tools >> make ${JOBS} >> make install >> popd >> >> # Prepare the gcc source code >> git clone git://sourceware.org/git/gcc.git --depth 1 >> pushd gcc >> git archive --format=tar.gz --prefix=gcc-13.0.0/ --output ../gcc-13.0.0.tar.gz "master" >> popd >> mv gcc-13.0.0.tar.gz ${DOWNLOADDIR} >> >> # Make and install the simplified GCC files >> tar xvf ${DOWNLOADDIR}/gcc-13.0.0.tar.gz -C ${BUILDDIR} >> pushd ${BUILDDIR}/gcc-13.0.0 >> mkdir tools-build >> pushd tools-build >> AR=ar LDFLAGS="-Wl,-rpath,${SYSDIR}/cross-tools/lib" \ >> ../configure --prefix=${SYSDIR}/cross-tools --build=${CROSS_HOST} --host=${CROSS_HOST} \ >> --target=${CROSS_TARGET} --disable-nls \ >> --with-mpfr=${SYSDIR}/cross-tools --with-gmp=${SYSDIR}/cross-tools \ >> --with-mpc=${SYSDIR}/cross-tools \ >> --with-newlib --disable-shared --with-sysroot=${SYSDIR}/sysroot \ >> --disable-decimal-float --disable-libgomp --disable-libitm \ >> --disable-libsanitizer --disable-libquadmath --disable-threads \ >> --disable-target-zlib --with-system-zlib --enable-checking=release \ >> --enable-default-pie \ >> --enable-languages=c >> make all-gcc all-target-libgcc ${JOBS} >> make install-strip-gcc install-strip-target-libgcc >> popd >> popd >> >> # Make and install the glibc files >> tar xvf ${DOWNLOADDIR}/glibc-2.36.tar.xz -C ${BUILDDIR} >> pushd ${BUILDDIR}/glibc-2.36 >> sed -i "s@5.15.0@4.15.0@g" sysdeps/unix/sysv/linux/loongarch/configure{,.ac} >> mkdir -v build-64 >> pushd build-64 >> BUILD_CC="gcc" CC="${CROSS_TARGET}-gcc ${BUILD64}" \ >> CXX="${CROSS_TARGET}-gcc ${BUILD64}" \ >> AR="${CROSS_TARGET}-ar" RANLIB="${CROSS_TARGET}-ranlib" \ >> ../configure --prefix=/usr --host=${CROSS_TARGET} --build=${CROSS_HOST} \ >> --libdir=/usr/lib64 --libexecdir=/usr/lib64/glibc \ >> --with-binutils=${SYSDIR}/cross-tools/bin \ >> --with-headers=${SYSDIR}/sysroot/usr/include \ >> --enable-stack-protector=strong --enable-add-ons \ >> --disable-werror libc_cv_slibdir=/usr/lib64 \ >> --enable-kernel=4.15 >> make ${JOBS} >> make DESTDIR=${SYSDIR}/sysroot install >> cp -v ../nscd/nscd.conf ${SYSDIR}/sysroot/etc/nscd.conf >> mkdir -pv ${SYSDIR}/sysroot/var/cache/nscd >> install -v -Dm644 ../nscd/nscd.tmpfiles \ >> ${SYSDIR}/sysroot/usr/lib/tmpfiles.d/nscd.conf >> install -v -Dm644 ../nscd/nscd.service \ >> ${SYSDIR}/sysroot/usr/lib/systemd/system/nscd.service >> popd >> mkdir -v build-locale >> pushd build-locale >> ../configure --prefix=/usr --libdir=/usr/lib64 --libexecdir=/usr/lib64/glibc \ >> --enable-stack-protector=strong --enable-add-ons \ >> --disable-werror libc_cv_slibdir=/usr/lib64 >> make ${JOBS} >> make DESTDIR=${SYSDIR}/sysroot localedata/install-locales >> popd >> popd >> >> # Make and install the complete GCC files >> tar xvf ${DOWNLOADDIR}/gcc-13.0.0.tar.gz -C ${BUILDDIR} >> pushd ${BUILDDIR}/gcc-13.0.0 >> mkdir tools-build-all >> pushd tools-build-all >> AR=ar LDFLAGS="-Wl,-rpath,${SYSDIR}/cross-tools/lib" \ >> ../configure --prefix=${SYSDIR}/cross-tools --build=${CROSS_HOST} \ >> --host=${CROSS_HOST} --target=${CROSS_TARGET} \ >> --with-sysroot=${SYSDIR}/sysroot --with-mpfr=${SYSDIR}/cross-tools \ >> --with-gmp=${SYSDIR}/cross-tools --with-mpc=${SYSDIR}/cross-tools \ >> --enable-__cxa_atexit --enable-threads=posix --with-system-zlib \ >> --enable-libstdcxx-time --enable-checking=release \ >> --enable-default-pie \ >> --enable-languages=c,c++,fortran,objc,obj-c++,lto >> make ${JOBS} >> make install-strip >> popd >> popd >> Thanks, -- Min Zhou > ^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH v7 0/7] Introduce support for LoongArch architecture 2022-09-30 14:20 ` David Marchand 2022-10-01 14:25 ` zhoumin @ 2022-10-03 8:14 ` Ali Alnubani 2022-10-03 12:44 ` zhoumin 1 sibling, 1 reply; 20+ messages in thread From: Ali Alnubani @ 2022-10-03 8:14 UTC (permalink / raw) To: David Marchand, zhoumin Cc: NBU-Contact-Thomas Monjalon (EXTERNAL), bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo, Aaron Conole, dpdklab, ci > -----Original Message----- > From: David Marchand <david.marchand@redhat.com> > Sent: Friday, September 30, 2022 5:21 PM > To: zhoumin <zhoumin@loongson.cn> > Cc: NBU-Contact-Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>; > bruce.richardson@intel.com; anatoly.burakov@intel.com; > qiming.yang@intel.com; Yuying.Zhang@intel.com; jgrajcia@cisco.com; > konstantin.v.ananyev@yandex.ru; dev@dpdk.org; maobibo@loongson.cn; > Aaron Conole <aconole@redhat.com>; Ali Alnubani <alialnu@nvidia.com>; > dpdklab <dpdklab@iol.unh.edu>; ci@dpdk.org > Subject: Re: [PATCH v7 0/7] Introduce support for LoongArch architecture > > On Fri, Sep 30, 2022 at 12:05 PM zhoumin <zhoumin@loongson.cn> wrote: > > On Fri, Sep 30, 2022 at 16:13, David Marchand wrote: > > > On Fri, Sep 30, 2022 at 10:02 AM Min Zhou <zhoumin@loongson.cn> > wrote: > > >> > > >> The online documents of LoongArch architecture are here: > > >> https://loongson.github.io/LoongArch-Documentation/README- > EN.html > > >> > > >> The latest build tools for LoongArch (binary) can be downloaded from: > > >> https://github.com/loongson/build-tools > > > Could you confirm which sources have been used to generate it? and > > > instructions to compile it? > > > > Only the cross compiler [1] is required. The instructions can be found in > > the new added file cross_build_dpdk_for_loongarch.rst. I had added the > > CI job for cross compiling DPDK for LoongArch in patch v7 7/7. The CI job > > can run successfully if without the GCC warning caused by vhost. > > - Sorry, but those instructions are not useful. > > Is this architecture support in upstream gcc not functional? > > Maybe I missed the information.. I spent some time at the different > links in the docs and in github, but I always end up with a set of > headers, or binaries, and no reference to the exact sources that were > used. > I have limited trust in binaries uploaded somewhere in github. > I don't want to spend more time on this. > > What I ask for, is clear instructions how to get the toolchain > sources, and how to generate this toolchain. > > > - About the vhost compilation issue, a fix in the same area of the > code is in progress. > It will take some time to get the fix. > I will postpone merging the last patch until the vhost fix is ready. > (I am rather confident all of this will be resolved by the time 22.11 > is released). > > > > > > >> v7: > > >> - rebase the patchset on the main repository > > >> - add errno.h to rte_power_intrinsics.c according with > > >> commit 72b452c5f259 > > > Thanks, I will look at this last revision. > > > > > > > > > There is still one aspect that is unclear to me. > > > How will the DPDK community make sure changes won't break this > > > architecture? (I mean, runtime checks, not only compilation) > > > IOW, what do you plan to hook to our CI to test patches submitted to > > > the mailing list? > > > > We can send our machine to UNH lab, but it may take a long time. > > > > GHA seems to be a good choice. However, I found that the codes of CI > > runner of GHA [2] are arch-specific. So the CI runner currently cannot > > run on > > LoongArch machine. > > I see. > > The better solution is probably to go with "your" own CI so that that > LoongArch has runtime non regression (functional and performance) > tests. > See below. > > > > > > Are there other CI clients which are not arch-specific and can be used > > for DPDK? > > We can provide machines accessible by the public network. These > machines run > > Loongnix-server system which was built based on the source rpms of > CentOS 8. > > We can deploy DPDK CI client on these machines. > > There is no "DPDK CI client" per se. > > The DPDK project has a distributed CI made of at least 3 CI entities. > > Those CI test patches and post reports via mail: the ovsrobot, Intel > CI and UNH lab. > A CI retrieves patches from patchwork, a set of scripts is available > in https://git.dpdk.org/tools/dpdk-ci/ (especially the poll-pw > script). > > Then the way the patches are tested is something each CI handles on its side: > - the ovsrobot creates a branch per series under the ovsrobot/dpdk > github repository, and let GitHub action run (this is how your current > series has been tested in GHA), > - Intel CI have their own tool for which I have little detail, > - UNH lab have their infrastructure too, using some Jenkins iirc. They > provide a dashboard for reports > https://lab.dpdk.org/results/dashboard/ and to get all details and > logs. > > The common point is that, at the end of testing a series, a test > report is sent to the (sender-restricted) test-report@ mailing list. > > Those reports could be done per patch, but given the amount of patches > on the dev@ mailing list, the consensus is to test the whole series > and report back against the last patch of a series. > > All of this is gathered by patchwork (the details of how it is done > are not 100% clear to me, maybe Ali can confirm later if a > modification is required). A few more things to add: Labs can either use "dpdk-ci:tools/poll-pw" to pull the patches/patchsets from the Events API endpoint (https://patches.dpdk.org/api/events), or they can use their own scripts. Events API objects should be filtered by the categories "patch-completed" or "series-completed". The script "dpdk-ci:tools/send-patch-report.sh" can be used to send reports to the mailing list in the expected report format. The dpdk.org servers take care of adding the report results to Patchwork once they are in the test-report archives. > > If you look at your v7 series, you will see: > https://patchwork.dpdk.org/project/dpdk/list/?series=24929&state=%2A&a > rchive=both > - ovsrobot: ci/github-robot link > http://mails.dpdk.org/archives/test-report/2022-September/310836.html > - Intel CI: ci/Intel-* links, for example on the compilation test > http://mails.dpdk.org/archives/test-report/2022-September/310822.html > - UNH lab: all ci/iol-* links, for example on the compilation test > http://mails.dpdk.org/archives/test-report/2022-September/310834.html > > So what LoongSoon could do is setup some Loongnix systems with a > similar infrastructure and provide (native?) compilation and runtime > test reports. > > I Cc'd a few people involved in all this. > And there is the ci@ mailing list where all CI people can discuss. > > > -- > David Marchand ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v7 0/7] Introduce support for LoongArch architecture 2022-10-03 8:14 ` Ali Alnubani @ 2022-10-03 12:44 ` zhoumin 0 siblings, 0 replies; 20+ messages in thread From: zhoumin @ 2022-10-03 12:44 UTC (permalink / raw) To: Ali Alnubani, David Marchand Cc: NBU-Contact-Thomas Monjalon (EXTERNAL), bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo, Aaron Conole, dpdklab, ci Hi, Ali, Thanks for your kind reply. On Mon, Oct 3, 2022 at 16:14, Ali Alnubani wrote: >> -----Original Message----- >> From: David Marchand <david.marchand@redhat.com> >> Sent: Friday, September 30, 2022 5:21 PM >> To: zhoumin <zhoumin@loongson.cn> >> Cc: NBU-Contact-Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>; >> bruce.richardson@intel.com; anatoly.burakov@intel.com; >> qiming.yang@intel.com; Yuying.Zhang@intel.com; jgrajcia@cisco.com; >> konstantin.v.ananyev@yandex.ru; dev@dpdk.org; maobibo@loongson.cn; >> Aaron Conole <aconole@redhat.com>; Ali Alnubani <alialnu@nvidia.com>; >> dpdklab <dpdklab@iol.unh.edu>; ci@dpdk.org >> Subject: Re: [PATCH v7 0/7] Introduce support for LoongArch architecture >> >> On Fri, Sep 30, 2022 at 12:05 PM zhoumin <zhoumin@loongson.cn> wrote: >>> On Fri, Sep 30, 2022 at 16:13, David Marchand wrote: >>>> On Fri, Sep 30, 2022 at 10:02 AM Min Zhou <zhoumin@loongson.cn> >> wrote: >>>>> The online documents of LoongArch architecture are here: >>>>> https://loongson.github.io/LoongArch-Documentation/README- >> EN.html >>>>> The latest build tools for LoongArch (binary) can be downloaded from: >>>>> https://github.com/loongson/build-tools >>>> Could you confirm which sources have been used to generate it? and >>>> instructions to compile it? >>> Only the cross compiler [1] is required. The instructions can be found in >>> the new added file cross_build_dpdk_for_loongarch.rst. I had added the >>> CI job for cross compiling DPDK for LoongArch in patch v7 7/7. The CI job >>> can run successfully if without the GCC warning caused by vhost. >> - Sorry, but those instructions are not useful. >> >> Is this architecture support in upstream gcc not functional? >> >> Maybe I missed the information.. I spent some time at the different >> links in the docs and in github, but I always end up with a set of >> headers, or binaries, and no reference to the exact sources that were >> used. >> I have limited trust in binaries uploaded somewhere in github. >> I don't want to spend more time on this. >> >> What I ask for, is clear instructions how to get the toolchain >> sources, and how to generate this toolchain. >> >> >> - About the vhost compilation issue, a fix in the same area of the >> code is in progress. >> It will take some time to get the fix. >> I will postpone merging the last patch until the vhost fix is ready. >> (I am rather confident all of this will be resolved by the time 22.11 >> is released). >> >> >>>>> v7: >>>>> - rebase the patchset on the main repository >>>>> - add errno.h to rte_power_intrinsics.c according with >>>>> commit 72b452c5f259 >>>> Thanks, I will look at this last revision. >>>> >>>> >>>> There is still one aspect that is unclear to me. >>>> How will the DPDK community make sure changes won't break this >>>> architecture? (I mean, runtime checks, not only compilation) >>>> IOW, what do you plan to hook to our CI to test patches submitted to >>>> the mailing list? >>> We can send our machine to UNH lab, but it may take a long time. >>> >>> GHA seems to be a good choice. However, I found that the codes of CI >>> runner of GHA [2] are arch-specific. So the CI runner currently cannot >>> run on >>> LoongArch machine. >> I see. >> >> The better solution is probably to go with "your" own CI so that that >> LoongArch has runtime non regression (functional and performance) >> tests. >> See below. >> >> >>> Are there other CI clients which are not arch-specific and can be used >>> for DPDK? >>> We can provide machines accessible by the public network. These >> machines run >>> Loongnix-server system which was built based on the source rpms of >> CentOS 8. >>> We can deploy DPDK CI client on these machines. >> There is no "DPDK CI client" per se. >> >> The DPDK project has a distributed CI made of at least 3 CI entities. >> >> Those CI test patches and post reports via mail: the ovsrobot, Intel >> CI and UNH lab. >> A CI retrieves patches from patchwork, a set of scripts is available >> in https://git.dpdk.org/tools/dpdk-ci/ (especially the poll-pw >> script). >> >> Then the way the patches are tested is something each CI handles on its side: >> - the ovsrobot creates a branch per series under the ovsrobot/dpdk >> github repository, and let GitHub action run (this is how your current >> series has been tested in GHA), >> - Intel CI have their own tool for which I have little detail, >> - UNH lab have their infrastructure too, using some Jenkins iirc. They >> provide a dashboard for reports >> https://lab.dpdk.org/results/dashboard/ and to get all details and >> logs. >> >> The common point is that, at the end of testing a series, a test >> report is sent to the (sender-restricted) test-report@ mailing list. >> >> Those reports could be done per patch, but given the amount of patches >> on the dev@ mailing list, the consensus is to test the whole series >> and report back against the last patch of a series. >> >> All of this is gathered by patchwork (the details of how it is done >> are not 100% clear to me, maybe Ali can confirm later if a >> modification is required). > A few more things to add: > Labs can either use "dpdk-ci:tools/poll-pw" to pull the patches/patchsets from the Events API endpoint (https://patches.dpdk.org/api/events), or they can use their own scripts. Events API objects should be filtered by the categories "patch-completed" or "series-completed". Yes! The scripts in the "dpdk-ci:tools/" are very useful, especially "poll-pw". We are building an internal CI system for LoongArch based on the dpdk-ci scripts and the Events API. > The script "dpdk-ci:tools/send-patch-report.sh" can be used to send reports to the mailing list in the expected report format. OK! It seems that the administer of mailing list should add the mail sender of LoongArch CI system to the whitelist. After that, the test reports from LoongArch CI system will not be blocked. > The dpdk.org servers take care of adding the report results to Patchwork once they are in the test-report archives. Thanks a lot. That is also my concerns. The dpdk.org servers are responsible for adding the report results to Patchwork. >> If you look at your v7 series, you will see: >> https://patchwork.dpdk.org/project/dpdk/list/?series=24929&state=%2A&a >> rchive=both >> - ovsrobot: ci/github-robot link >> http://mails.dpdk.org/archives/test-report/2022-September/310836.html >> - Intel CI: ci/Intel-* links, for example on the compilation test >> http://mails.dpdk.org/archives/test-report/2022-September/310822.html >> - UNH lab: all ci/iol-* links, for example on the compilation test >> http://mails.dpdk.org/archives/test-report/2022-September/310834.html >> >> So what LoongSoon could do is setup some Loongnix systems with a >> similar infrastructure and provide (native?) compilation and runtime >> test reports. >> >> I Cc'd a few people involved in all this. >> And there is the ci@ mailing list where all CI people can discuss. >> >> >> -- >> David Marchand ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v7 0/7] Introduce support for LoongArch architecture 2022-09-30 8:02 [PATCH v7 0/7] Introduce support for LoongArch architecture Min Zhou ` (7 preceding siblings ...) 2022-09-30 8:13 ` [PATCH v7 0/7] Introduce support for LoongArch architecture David Marchand @ 2022-10-04 6:59 ` David Marchand 2022-10-04 8:50 ` zhoumin 8 siblings, 1 reply; 20+ messages in thread From: David Marchand @ 2022-10-04 6:59 UTC (permalink / raw) To: Min Zhou Cc: thomas, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo On Fri, Sep 30, 2022 at 10:02 AM Min Zhou <zhoumin@loongson.cn> wrote: > > Dear team, > > The following patch set is intended to support DPDK running on LoongArch > architecture. > > LoongArch is the general processor architecture of Loongson Corporation > and is a new RISC ISA, which is a bit like MIPS or RISC-V. > > The online documents of LoongArch architecture are here: > https://loongson.github.io/LoongArch-Documentation/README-EN.html > > The latest build tools for LoongArch (binary) can be downloaded from: > https://github.com/loongson/build-tools > > v7: > - rebase the patchset on the main repository > - add errno.h to rte_power_intrinsics.c according with > commit 72b452c5f259 I did some comments on patch 1. I am still considering the patch 7 (hooking into GHA) but the rest looks good enough to me. Could you respin the series? Thanks! -- David Marchand ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v7 0/7] Introduce support for LoongArch architecture 2022-10-04 6:59 ` David Marchand @ 2022-10-04 8:50 ` zhoumin 0 siblings, 0 replies; 20+ messages in thread From: zhoumin @ 2022-10-04 8:50 UTC (permalink / raw) To: David Marchand Cc: thomas, bruce.richardson, anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev, dev, maobibo On Tue, Oct 4, 2022 at 14:59, David Marchand wrote: > On Fri, Sep 30, 2022 at 10:02 AM Min Zhou <zhoumin@loongson.cn> wrote: >> Dear team, >> >> The following patch set is intended to support DPDK running on LoongArch >> architecture. >> >> LoongArch is the general processor architecture of Loongson Corporation >> and is a new RISC ISA, which is a bit like MIPS or RISC-V. >> >> The online documents of LoongArch architecture are here: >> https://loongson.github.io/LoongArch-Documentation/README-EN.html >> >> The latest build tools for LoongArch (binary) can be downloaded from: >> https://github.com/loongson/build-tools >> >> v7: >> - rebase the patchset on the main repository >> - add errno.h to rte_power_intrinsics.c according with >> commit 72b452c5f259 > I did some comments on patch 1. Yes, thanks. I have read them carefully and prepare to send the v8 patchset. > I am still considering the patch 7 (hooking into GHA) but the rest > looks good enough to me. Yes, thanks. The changes in the patch 7 is indeed not good for adding CI for LoongArch. As we discussed last weekend, it is better to set up a CI system for LoongArch and integrate the test results of new patch to Patchwork. We are building the CI system, but it will take some time. > Could you respin the series? OK, thank. I will send the v8 patchset to fix them. > > Thanks! Thanks, -- Min Zhou ^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-10-04 8:50 UTC | newest] Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-09-30 8:02 [PATCH v7 0/7] Introduce support for LoongArch architecture Min Zhou 2022-09-30 8:02 ` [PATCH v7 1/7] eal/loongarch: support " Min Zhou 2022-10-03 17:15 ` David Marchand 2022-10-04 8:49 ` zhoumin 2022-09-30 8:02 ` [PATCH v7 2/7] net/ixgbe: add vector stubs for LoongArch Min Zhou 2022-09-30 8:02 ` [PATCH v7 3/7] net/memif: set memfd syscall ID on LoongArch Min Zhou 2022-09-30 8:02 ` [PATCH v7 4/7] net/tap: set BPF syscall ID for LoongArch Min Zhou 2022-09-30 8:02 ` [PATCH v7 5/7] examples/l3fwd: enable LoongArch operation Min Zhou 2022-09-30 8:02 ` [PATCH v7 6/7] test/cpuflags: add test for LoongArch cpu flag Min Zhou 2022-09-30 8:02 ` [PATCH v7 7/7] ci: add LOONGARCH64 cross compilation job Min Zhou 2022-09-30 8:13 ` [PATCH v7 0/7] Introduce support for LoongArch architecture David Marchand 2022-09-30 10:05 ` zhoumin 2022-09-30 14:20 ` David Marchand 2022-10-01 14:25 ` zhoumin 2022-10-03 16:30 ` David Marchand 2022-10-04 8:49 ` zhoumin 2022-10-03 8:14 ` Ali Alnubani 2022-10-03 12:44 ` zhoumin 2022-10-04 6:59 ` David Marchand 2022-10-04 8:50 ` zhoumin
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