From: Arek Kusztal <arkadiuszx.kusztal@intel.com>
To: dev@dpdk.org
Cc: gakhil@marvell.com, kai.ji@intel.com,
Arek Kusztal <arkadiuszx.kusztal@intel.com>
Subject: [PATCH v2 1/2] crypto/qat: add SM4 encryption algorithm
Date: Fri, 30 Sep 2022 10:41:07 +0100 [thread overview]
Message-ID: <20220930094108.6406-2-arkadiuszx.kusztal@intel.com> (raw)
In-Reply-To: <20220930094108.6406-1-arkadiuszx.kusztal@intel.com>
- Added ShangMi 4 (SM4) encryption algorithms.
Supported modes: ECB, CBC, CTR.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
doc/guides/cryptodevs/features/qat.ini | 3 +++
doc/guides/rel_notes/release_22_11.rst | 4 ++++
drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 9 +++++++++
drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 9 +++++++++
drivers/crypto/qat/qat_sym_session.c | 12 ++++++++++++
5 files changed, 37 insertions(+)
diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini
index b9755a757e..edabc030d7 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -40,6 +40,9 @@ KASUMI F8 = Y
AES DOCSIS BPI = Y
DES DOCSIS BPI = Y
ZUC EEA3 = Y
+SM4 ECB = Y
+SM4 CBC = Y
+SM4 CTR = Y
;
; Supported authentication algorithms of the 'qat' crypto driver.
;
diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst
index d6278f1ff0..42aba19af7 100644
--- a/doc/guides/rel_notes/release_22_11.rst
+++ b/doc/guides/rel_notes/release_22_11.rst
@@ -105,6 +105,10 @@ New Features
Added ``RTE_CRYPTO_AUTH_SM3`` to the auth algorithm list in the cryptodev.
+* **Updated the Intel QuickAssist Technology (QAT) symmetric crypto PMD.**
+
+ Added SM4 encryption algorithm to the QAT PMD.
+ Supported modes are ECB, CBC and CTR.
Removed Items
-------------
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
index 2d5f10aeac..d1285cdbd4 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
@@ -131,6 +131,15 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen3[] = {
CAP_RNG(key_size, 32, 32, 0),
CAP_RNG(digest_size, 16, 16, 0),
CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)),
+ QAT_SYM_CIPHER_CAP(SM4_ECB,
+ CAP_SET(block_size, 16),
+ CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 0, 0, 0)),
+ QAT_SYM_CIPHER_CAP(SM4_CBC,
+ CAP_SET(block_size, 16),
+ CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
+ QAT_SYM_CIPHER_CAP(SM4_CTR,
+ CAP_SET(block_size, 16),
+ CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
index a9457d9278..efbbbda4b6 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
@@ -91,6 +91,15 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = {
CAP_RNG(key_size, 32, 32, 0),
CAP_RNG(digest_size, 16, 16, 0),
CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)),
+ QAT_SYM_CIPHER_CAP(SM4_ECB,
+ CAP_SET(block_size, 16),
+ CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 0, 0, 0)),
+ QAT_SYM_CIPHER_CAP(SM4_CBC,
+ CAP_SET(block_size, 16),
+ CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
+ QAT_SYM_CIPHER_CAP(SM4_CTR,
+ CAP_SET(block_size, 16),
+ CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 52b3455cf0..68a38aa69b 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -465,6 +465,18 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,
}
session->qat_mode = ICP_QAT_HW_CIPHER_XTS_MODE;
break;
+ case RTE_CRYPTO_CIPHER_SM4_ECB:
+ session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4;
+ session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
+ break;
+ case RTE_CRYPTO_CIPHER_SM4_CBC:
+ session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4;
+ session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
+ break;
+ case RTE_CRYPTO_CIPHER_SM4_CTR:
+ session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4;
+ session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
+ break;
case RTE_CRYPTO_CIPHER_3DES_ECB:
case RTE_CRYPTO_CIPHER_AES_ECB:
case RTE_CRYPTO_CIPHER_AES_F8:
--
2.13.6
next prev parent reply other threads:[~2022-09-30 10:50 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 9:41 [PATCH v2 0/2] crypto/qat: add sm3 and sm4 algorithms Arek Kusztal
2022-09-30 9:41 ` Arek Kusztal [this message]
2022-09-30 9:41 ` [PATCH v2 2/2] crypto/qat : add SM3 hash algorithm Arek Kusztal
2022-09-30 17:44 ` [EXT] [PATCH v2 0/2] crypto/qat: add sm3 and sm4 algorithms Akhil Goyal
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