From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8DCB7A0542; Tue, 4 Oct 2022 19:17:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EAF8842905; Tue, 4 Oct 2022 19:17:12 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id D0822427EE for ; Tue, 4 Oct 2022 19:17:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664903830; x=1696439830; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SDLuC2MBrtA0LF7naxVWBqxP1bRr+sVhmg6BHBzTYKc=; b=Q7yjjewH9YoPLFPdGRwPUe+jVqc5+IInSdU/Si7hWsfGV6vRW9NGZNoD PdzhZa4Z/WbFeuVenwWd30ArAdFMMUFuFTNWxLH9lrYtO5TdY7uaKS3dC mkB8jf0mbrh7fLEcNzWl6vc6It6ThQAUz4mUNbe8FXOkGh2LN5a/4FFyY fn6Q0Sm/RIw9ptoXtxxlbtdwFLgSeBdDXF9cNGMpTZjMyVTyJ++6ac89p w7gy47HbQd3IMytj1TDuCYRDE+xieyXIcWaZg3B67i2PQiLzebYYompp6 XGU2G3A4uTGWgnD2ECdJPKWUE13aX7/b5b/8S3QGNH44taycollA+OHpO w==; X-IronPort-AV: E=McAfee;i="6500,9779,10490"; a="290192278" X-IronPort-AV: E=Sophos;i="5.95,158,1661842800"; d="scan'208";a="290192278" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2022 10:17:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10490"; a="626256647" X-IronPort-AV: E=Sophos;i="5.95,158,1661842800"; d="scan'208";a="626256647" Received: from unknown (HELO icx-npg-scs1-cp1.localdomain) ([10.233.180.245]) by fmsmga007.fm.intel.com with ESMTP; 04 Oct 2022 10:17:06 -0700 From: Nicolas Chautru To: dev@dpdk.org, thomas@monjalon.net, gakhil@marvell.com Cc: maxime.coquelin@redhat.com, trix@redhat.com, mdr@ashroe.eu, bruce.richardson@intel.com, david.marchand@redhat.com, stephen@networkplumber.org, mingshan.zhang@intel.com, hemant.agrawal@nxp.com, Nicolas Chautru Subject: [PATCH v12 4/7] drivers/baseband: update PMDs to expose queue per operation Date: Tue, 4 Oct 2022 10:16:53 -0700 Message-Id: <20221004171656.17967-5-nicolas.chautru@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221004171656.17967-1-nicolas.chautru@intel.com> References: <1655491040-183649-6-git-send-email-nicolas.chautru@intel.com> <20221004171656.17967-1-nicolas.chautru@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support in existing bbdev PMDs for the explicit number of queues and priority for each operation type configured on the device. Signed-off-by: Nicolas Chautru Acked-by: Maxime Coquelin Acked-by: Hemant Agrawal --- drivers/baseband/acc100/rte_acc100_pmd.c | 29 +++++++++++-------- .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 8 +++++ drivers/baseband/fpga_lte_fec/fpga_lte_fec.c | 8 +++++ drivers/baseband/la12xx/bbdev_la12xx.c | 7 +++++ .../baseband/turbo_sw/bbdev_turbo_software.c | 12 ++++++++ 5 files changed, 52 insertions(+), 12 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index cdabc0f879..10272fd149 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -967,6 +967,7 @@ acc100_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info) { struct acc100_device *d = dev->data->dev_private; + int i; static const struct rte_bbdev_op_cap bbdev_capabilities[] = { { @@ -1063,19 +1064,23 @@ acc100_dev_info_get(struct rte_bbdev *dev, fetch_acc100_config(dev); dev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED; - /* This isn't ideal because it reports the maximum number of queues but - * does not provide info on how many can be uplink/downlink or different - * priorities - */ - dev_info->max_num_queues = - d->acc100_conf.q_dl_5g.num_aqs_per_groups * - d->acc100_conf.q_dl_5g.num_qgroups + - d->acc100_conf.q_ul_5g.num_aqs_per_groups * - d->acc100_conf.q_ul_5g.num_qgroups + - d->acc100_conf.q_dl_4g.num_aqs_per_groups * - d->acc100_conf.q_dl_4g.num_qgroups + - d->acc100_conf.q_ul_4g.num_aqs_per_groups * + /* Expose number of queues */ + dev_info->num_queues[RTE_BBDEV_OP_NONE] = 0; + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = d->acc100_conf.q_ul_4g.num_aqs_per_groups * d->acc100_conf.q_ul_4g.num_qgroups; + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = d->acc100_conf.q_dl_4g.num_aqs_per_groups * + d->acc100_conf.q_dl_4g.num_qgroups; + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] = d->acc100_conf.q_ul_5g.num_aqs_per_groups * + d->acc100_conf.q_ul_5g.num_qgroups; + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = d->acc100_conf.q_dl_5g.num_aqs_per_groups * + d->acc100_conf.q_dl_5g.num_qgroups; + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] = d->acc100_conf.q_ul_4g.num_qgroups; + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] = d->acc100_conf.q_dl_4g.num_qgroups; + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = d->acc100_conf.q_ul_5g.num_qgroups; + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = d->acc100_conf.q_dl_5g.num_qgroups; + dev_info->max_num_queues = 0; + for (i = RTE_BBDEV_OP_TURBO_DEC; i <= RTE_BBDEV_OP_LDPC_ENC; i++) + dev_info->max_num_queues += dev_info->num_queues[i]; dev_info->queue_size_lim = ACC100_MAX_QUEUE_DEPTH; dev_info->hardware_accelerated = true; dev_info->max_dl_queue_priority = diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c index 3c36d09730..d520d5238f 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c @@ -379,6 +379,14 @@ fpga_dev_info_get(struct rte_bbdev *dev, if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) dev_info->max_num_queues++; } + /* Expose number of queue per operation type */ + dev_info->num_queues[RTE_BBDEV_OP_NONE] = 0; + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = 0; + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = 0; + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] = dev_info->max_num_queues / 2; + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = dev_info->max_num_queues / 2; + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = 1; + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = 1; } /** diff --git a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c index 67b44992b2..fc86f13bee 100644 --- a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c +++ b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c @@ -655,6 +655,14 @@ fpga_dev_info_get(struct rte_bbdev *dev, if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) dev_info->max_num_queues++; } + /* Expose number of queue per operation type */ + dev_info->num_queues[RTE_BBDEV_OP_NONE] = 0; + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = dev_info->max_num_queues / 2; + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = dev_info->max_num_queues / 2; + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] = 0; + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = 0; + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] = 1; + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] = 1; } /** diff --git a/drivers/baseband/la12xx/bbdev_la12xx.c b/drivers/baseband/la12xx/bbdev_la12xx.c index 11a385ef56..bb754a5395 100644 --- a/drivers/baseband/la12xx/bbdev_la12xx.c +++ b/drivers/baseband/la12xx/bbdev_la12xx.c @@ -103,6 +103,13 @@ la12xx_info_get(struct rte_bbdev *dev __rte_unused, dev_info->min_alignment = 64; dev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED; + dev_info->num_queues[RTE_BBDEV_OP_NONE] = 0; + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = 0; + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = 0; + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] = LA12XX_MAX_QUEUES / 2; + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = LA12XX_MAX_QUEUES / 2; + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = 1; + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = 1; rte_bbdev_log_debug("got device info from %u", dev->data->dev_id); } diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c index 98489d218b..7afa298848 100644 --- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c +++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c @@ -158,6 +158,8 @@ static void info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info) { struct bbdev_private *internals = dev->data->dev_private; + const struct rte_bbdev_op_cap *op_cap; + int num_op_type = 0; static const struct rte_bbdev_op_cap bbdev_capabilities[] = { #ifdef RTE_BBDEV_SDK_AVX2 @@ -257,6 +259,16 @@ info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info) dev_info->data_endianness = RTE_LITTLE_ENDIAN; dev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED; + op_cap = bbdev_capabilities; + for (; op_cap->type != RTE_BBDEV_OP_NONE; ++op_cap) + num_op_type++; + op_cap = bbdev_capabilities; + if (num_op_type > 0) { + int num_queue_per_type = dev_info->max_num_queues / num_op_type; + for (; op_cap->type != RTE_BBDEV_OP_NONE; ++op_cap) + dev_info->num_queues[op_cap->type] = num_queue_per_type; + } + rte_bbdev_log_debug("got device info from %u\n", dev->data->dev_id); } -- 2.37.1