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From: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
	Kiran Kumar K <kirankumark@marvell.com>,
	Sunil Kumar Kori <skori@marvell.com>,
	Satha Rao <skoteshwar@marvell.com>
Cc: dev@dpdk.org, Hanumanth Pothula <hpothula@marvell.com>
Subject: [PATCH v8 3/4] net/cnxk: support mulitiple mbuf pools per Rx queue
Date: Fri,  7 Oct 2022 20:29:20 +0300	[thread overview]
Message-ID: <20221007172921.3325250-4-andrew.rybchenko@oktetlabs.ru> (raw)
In-Reply-To: <20221007172921.3325250-1-andrew.rybchenko@oktetlabs.ru>

From: Hanumanth Pothula <hpothula@marvell.com>

Presently, HW is programmed only to receive packets from LPB pool.
Making all packets received from LPB pool.

But, CNXK HW supports two pools,
 - SPB -> packets with smaller size (less than 4K)
 - LPB -> packets with bigger size (greater than 4K)

Patch enables multiple mempool capability, pool is selected based
on the packet's length. So, basically, PMD programs HW for receiving
packets from both SPB and LPB pools based on the packet's length.

This is achieved by enabling rx multiple mempool offload,
RTE_ETH_RX_OFFLOAD_MUL_MEMPOOL. This allows the application to send
more than one pool(in our case two) to the driver, with different
segment(packet) lengths, which helps the driver to configure both
pools based on segment lengths.

This is often useful for saving the memory where the application
can create a different pool to steer the specific size of the
packet, thus enabling effective use of memory.

Signed-off-by: Hanumanth Pothula <hpothula@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c     | 84 ++++++++++++++++++++++++++----
 drivers/net/cnxk/cnxk_ethdev.h     |  2 +
 drivers/net/cnxk/cnxk_ethdev_ops.c |  3 ++
 3 files changed, 80 insertions(+), 9 deletions(-)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 2cb48ba152..bb27cc87fd 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -541,6 +541,58 @@ cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)
 	plt_free(txq_sp);
 }
 
+static int
+cnxk_nix_process_rx_conf(const struct rte_eth_rxconf *rx_conf,
+			 struct rte_mempool **lpb_pool,
+			 struct rte_mempool **spb_pool)
+{
+	struct rte_mempool *pool0;
+	struct rte_mempool *pool1;
+	struct rte_mempool **mp = rx_conf->rx_mempools;
+	const char *platform_ops;
+	struct rte_mempool_ops *ops;
+
+	if (*lpb_pool ||
+	    rx_conf->rx_nmempool != CNXK_NIX_NUM_POOLS_MAX) {
+		plt_err("invalid arguments");
+		return -EINVAL;
+	}
+
+	if (mp == NULL || mp[0] == NULL || mp[1] == NULL) {
+		plt_err("invalid memory pools\n");
+		return -EINVAL;
+	}
+
+	pool0 = mp[0];
+	pool1 = mp[1];
+
+	if (pool0->elt_size > pool1->elt_size) {
+		*lpb_pool = pool0;
+		*spb_pool = pool1;
+
+	} else {
+		*lpb_pool = pool1;
+		*spb_pool = pool0;
+	}
+
+	if ((*spb_pool)->pool_id == 0) {
+		plt_err("Invalid pool_id");
+		return -EINVAL;
+	}
+
+	platform_ops = rte_mbuf_platform_mempool_ops();
+	ops = rte_mempool_get_ops((*spb_pool)->ops_index);
+	if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
+		plt_err("mempool ops should be of cnxk_npa type");
+		return -EINVAL;
+	}
+
+	plt_info("spb_pool:%s lpb_pool:%s lpb_len:%u spb_len:%u\n", (*spb_pool)->name,
+		 (*lpb_pool)->name, (*lpb_pool)->elt_size, (*spb_pool)->elt_size);
+
+	return 0;
+}
+
 int
 cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 			uint32_t nb_desc, uint16_t fp_rx_q_sz,
@@ -557,6 +609,8 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 	uint16_t first_skip;
 	int rc = -EINVAL;
 	size_t rxq_sz;
+	struct rte_mempool *lpb_pool = mp;
+	struct rte_mempool *spb_pool = NULL;
 
 	/* Sanity checks */
 	if (rx_conf->rx_deferred_start == 1) {
@@ -564,15 +618,21 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 		goto fail;
 	}
 
+	if (rx_conf->rx_nmempool > 0) {
+		rc = cnxk_nix_process_rx_conf(rx_conf, &lpb_pool, &spb_pool);
+		if (rc)
+			goto fail;
+	}
+
 	platform_ops = rte_mbuf_platform_mempool_ops();
 	/* This driver needs cnxk_npa mempool ops to work */
-	ops = rte_mempool_get_ops(mp->ops_index);
+	ops = rte_mempool_get_ops(lpb_pool->ops_index);
 	if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
 		plt_err("mempool ops should be of cnxk_npa type");
 		goto fail;
 	}
 
-	if (mp->pool_id == 0) {
+	if (lpb_pool->pool_id == 0) {
 		plt_err("Invalid pool_id");
 		goto fail;
 	}
@@ -589,13 +649,13 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 	/* Its a no-op when inline device is not used */
 	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY ||
 	    dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
-		roc_nix_inl_dev_xaq_realloc(mp->pool_id);
+		roc_nix_inl_dev_xaq_realloc(lpb_pool->pool_id);
 
 	/* Increase CQ size to Aura size to avoid CQ overflow and
 	 * then CPT buffer leak.
 	 */
 	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
-		nb_desc = nix_inl_cq_sz_clamp_up(nix, mp, nb_desc);
+		nb_desc = nix_inl_cq_sz_clamp_up(nix, lpb_pool, nb_desc);
 
 	/* Setup ROC CQ */
 	cq = &dev->cqs[qid];
@@ -611,17 +671,17 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 	rq = &dev->rqs[qid];
 	rq->qid = qid;
 	rq->cqid = cq->qid;
-	rq->aura_handle = mp->pool_id;
+	rq->aura_handle = lpb_pool->pool_id;
 	rq->flow_tag_width = 32;
 	rq->sso_ena = false;
 
 	/* Calculate first mbuf skip */
 	first_skip = (sizeof(struct rte_mbuf));
 	first_skip += RTE_PKTMBUF_HEADROOM;
-	first_skip += rte_pktmbuf_priv_size(mp);
+	first_skip += rte_pktmbuf_priv_size(lpb_pool);
 	rq->first_skip = first_skip;
 	rq->later_skip = sizeof(struct rte_mbuf);
-	rq->lpb_size = mp->elt_size;
+	rq->lpb_size = lpb_pool->elt_size;
 	if (roc_errata_nix_no_meta_aura())
 		rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);
 
@@ -629,6 +689,12 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 	if (roc_nix_inl_inb_is_enabled(nix))
 		rq->ipsech_ena = true;
 
+	if (spb_pool) {
+		rq->spb_ena = 1;
+		rq->spb_aura_handle = spb_pool->pool_id;
+		rq->spb_size = spb_pool->elt_size;
+	}
+
 	rc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);
 	if (rc) {
 		plt_err("Failed to init roc rq for rq=%d, rc=%d", qid, rc);
@@ -651,7 +717,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 	/* Queue config should reflect global offloads */
 	rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;
 	rxq_sp->qconf.nb_desc = nb_desc;
-	rxq_sp->qconf.mp = mp;
+	rxq_sp->qconf.mp = lpb_pool;
 	rxq_sp->tc = 0;
 	rxq_sp->tx_pause = (dev->fc_cfg.mode == RTE_ETH_FC_FULL ||
 			    dev->fc_cfg.mode == RTE_ETH_FC_TX_PAUSE);
@@ -670,7 +736,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 			goto free_mem;
 	}
 
-	plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, mp->name, nb_desc,
+	plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, lpb_pool->name, nb_desc,
 		    cq->nb_desc);
 
 	/* Store start of fast path area */
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 5204c46244..d282f79a9a 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -44,6 +44,8 @@
 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
 /* Max supported SQB count */
 #define CNXK_NIX_TX_MAX_SQB 512
+/* LPB & SPB */
+#define CNXK_NIX_NUM_POOLS_MAX 2
 
 /* If PTP is enabled additional SEND MEM DESC is required which
  * takes 2 words, hence max 7 iova address are possible
diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c
index 30d169f799..8f7287161b 100644
--- a/drivers/net/cnxk/cnxk_ethdev_ops.c
+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c
@@ -69,6 +69,9 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
 	devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 			    RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP |
 			    RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
+
+	devinfo->max_rx_mempools = CNXK_NIX_NUM_POOLS_MAX;
+
 	return 0;
 }
 
-- 
2.30.2


  parent reply	other threads:[~2022-10-07 17:29 UTC|newest]

Thread overview: 75+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-12 10:46 [PATCH v1 1/1] ethdev: introduce pool sort capability Hanumanth Pothula
2022-08-12 13:27 ` Morten Brørup
2022-08-12 17:24 ` [PATCH v2 1/3] " Hanumanth Pothula
2022-08-12 17:24   ` [PATCH v2 2/3] app/testpmd: add command line argument 'rxseg-mode' Hanumanth Pothula
2022-08-12 17:24   ` [PATCH v2 3/3] net/cnxk: introduce pool sort capability Hanumanth Pothula
2022-08-23  3:26   ` [PATCH v2 1/3] ethdev: " Ding, Xuan
2022-08-24 15:33     ` Ferruh Yigit
2022-08-30 12:08       ` [EXT] " Hanumanth Reddy Pothula
2022-09-06 12:18         ` Ferruh Yigit
2022-09-07  7:02           ` Hanumanth Reddy Pothula
2022-09-07 11:24             ` Ferruh Yigit
2022-09-07 21:31               ` Hanumanth Reddy Pothula
2022-09-13  9:28                 ` Ferruh Yigit
2022-09-13 10:00                   ` Hanumanth Reddy Pothula
2022-09-02  7:00   ` [PATCH v3 " Hanumanth Pothula
2022-09-02  7:00     ` [PATCH v3 2/3] app/testpmd: Add support for " Hanumanth Pothula
2022-09-02  7:00     ` [PATCH v3 3/3] net/cnxk: introduce " Hanumanth Pothula
2022-09-13  8:06     ` [PATCH v3 1/3] ethdev: " Andrew Rybchenko
2022-09-13  9:31       ` Ferruh Yigit
2022-09-13 10:41         ` [EXT] " Hanumanth Reddy Pothula
2022-09-15  7:07     ` [PATCH v4 1/3] ethdev: Add support for mulitiple mbuf pools per Rx queue Hanumanth Pothula
2022-09-15  7:07       ` [PATCH v4 2/3] app/testpmd: " Hanumanth Pothula
2022-09-15  7:07       ` [PATCH v4 3/3] net/cnxk: Add support for mulitiple mbuf pools Hanumanth Pothula
2022-09-28  9:43       ` [PATCH v4 1/3] ethdev: Add support for mulitiple mbuf pools per Rx queue Andrew Rybchenko
2022-09-28 11:06         ` Thomas Monjalon
2022-10-06 17:01       ` [PATCH v5 1/3] ethdev: support " Hanumanth Pothula
2022-10-06 17:01         ` [PATCH v5 2/3] net/cnxk: " Hanumanth Pothula
2022-10-06 17:01         ` [PATCH v5 3/3] app/testpmd: " Hanumanth Pothula
2022-10-06 17:29         ` [PATCH v5 1/3] ethdev: " Stephen Hemminger
2022-10-07 14:13           ` Andrew Rybchenko
2022-10-06 17:53         ` [PATCH v6 " Hanumanth Pothula
2022-10-06 17:53           ` [PATCH v6 2/3] net/cnxk: " Hanumanth Pothula
2022-10-06 17:53           ` [PATCH v6 3/3] app/testpmd: " Hanumanth Pothula
2022-10-06 18:14           ` [PATCH v6 1/3] ethdev: " Hanumanth Reddy Pothula
2022-10-07 14:37         ` [PATCH v7 0/4] " Andrew Rybchenko
2022-10-07 14:37           ` [PATCH v7 1/4] ethdev: factor out helper function to check Rx mempool Andrew Rybchenko
2022-10-07 14:37           ` [PATCH v7 2/4] ethdev: support mulitiple mbuf pools per Rx queue Andrew Rybchenko
2022-10-07 16:08             ` Thomas Monjalon
2022-10-07 16:18               ` Stephen Hemminger
2022-10-07 16:20                 ` Stephen Hemminger
2022-10-07 16:33                   ` Andrew Rybchenko
2022-10-07 17:30               ` Andrew Rybchenko
2022-10-07 14:37           ` [PATCH v7 3/4] net/cnxk: " Andrew Rybchenko
2022-10-07 14:37           ` [PATCH v7 4/4] app/testpmd: " Andrew Rybchenko
2022-10-07 17:29         ` [PATCH v8 0/4] ethdev: " Andrew Rybchenko
2022-10-07 17:29           ` [PATCH v8 1/4] ethdev: factor out helper function to check Rx mempool Andrew Rybchenko
2022-10-07 17:29           ` [PATCH v8 2/4] ethdev: support multiple mbuf pools per Rx queue Andrew Rybchenko
2022-10-07 18:35             ` Thomas Monjalon
2022-10-07 19:45               ` Andrew Rybchenko
2022-10-07 17:29           ` Andrew Rybchenko [this message]
2022-10-07 17:29           ` [PATCH v8 4/4] app/testpmd: support mulitiple " Andrew Rybchenko
     [not found]             ` <PH0PR18MB47500560DC1793F68E7312DDCB5F9@PH0PR18MB4750.namprd18.prod.outlook.com>
2022-10-07 19:43               ` [EXT] " Andrew Rybchenko
2022-10-07 19:56                 ` Hanumanth Reddy Pothula
2022-10-17  8:48             ` [PATCH v9 1/1] " Hanumanth Pothula
2022-10-21 15:57               ` Singh, Aman Deep
2022-10-24  3:32                 ` [EXT] " Hanumanth Reddy Pothula
2022-10-24  4:07               ` [PATCH v10 1/1] app/testpmd: support multiple " Hanumanth Pothula
2022-10-25  1:40                 ` [PATCH v11 " Hanumanth Pothula
2022-11-01 14:13                   ` Hanumanth Reddy Pothula
2022-11-03 12:15                   ` Singh, Aman Deep
2022-11-03 12:36                     ` [EXT] " Hanumanth Reddy Pothula
2022-11-03 15:20                       ` Singh, Aman Deep
2022-11-04 15:38                         ` Hanumanth Reddy Pothula
2022-11-07  5:31                   ` [PATCH v12 " Hanumanth Pothula
2022-11-09  8:04                     ` Singh, Aman Deep
2022-11-09 10:39                       ` Andrew Rybchenko
2022-11-10  6:51                         ` Andrew Rybchenko
2022-11-10  8:17                     ` [PATCH v13 " Hanumanth Pothula
2022-11-10  9:01                       ` Andrew Rybchenko
2022-11-10  9:31                         ` [EXT] " Hanumanth Reddy Pothula
2022-11-10 10:16                       ` [PATCH v14 " Hanumanth Pothula
2022-11-10 10:47                         ` Andrew Rybchenko
2022-11-17  8:43                         ` Jiang, YuX
2022-11-17 11:38                           ` Hanumanth Reddy Pothula
2022-10-08 20:38           ` [PATCH v8 0/4] ethdev: support mulitiple " Thomas Monjalon

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