From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8734DA0542; Sat, 8 Oct 2022 10:38:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EB20242B7C; Sat, 8 Oct 2022 10:38:51 +0200 (CEST) Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) by mails.dpdk.org (Postfix) with ESMTP id C4AB442B77 for ; Sat, 8 Oct 2022 10:38:50 +0200 (CEST) Received: by mail-pl1-f169.google.com with SMTP id 10so6514363pli.0 for ; Sat, 08 Oct 2022 01:38:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JkDnZ4RKTUrRQvxgfNNTRS+X4VFlzi2+BZbyWGbTG4Q=; b=y/MAttaO4dF4Js4JEqiHp/aMyhnLncZH3zH51gMwhzo12E1V6JxPYNxSFomX6rKJyP UkD/yq4MjWGHrqoff/+g06gekgEaQgYc0xNnzwcNxgpn+ohHtFoiKb4gVYcj5n8nvle1 Czpe9UtlAYetYohFt6uuwQzCf9fzvUZlY10V9cXLXm/nBtBzHFaI0DknliXhUXFqa4Yb tko+d4rlKmLgAS65iJOEfdvUwLbi4UFdSTsYPF/CaMQvt6AE1qJpwHaxpeQwCgGsZ5yw PjS3thNlXgW5Kkrgg7M19UTKBmy/UuhkdvyVm8cHNICw8Idv6t5r2NzWFydH9QGozDmn EtYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JkDnZ4RKTUrRQvxgfNNTRS+X4VFlzi2+BZbyWGbTG4Q=; b=5SJzZpgmRTIJpzT2lxnxCVZmiz3IgQMhKXorXAhLsO1Yyzsc0O5bHmRr/leeSmWonn NpwffwTYqgEBCXxU1V2W4u47qn3nW5BGYN6iE7zAVfsM9gvIm/oJbTka5bFjMOYGiU+L x/3qGmqbe0BdlEgwtnQLS1RpegAg+U8KIAp3KZKrt5YdSyOwkFbasFCAFpm8qC2Z3zcI Z0cHuBB2tiNFOidTvcU+7RVG/TM1D4j1IE9lsa5Yiip5XmVBpQthpkFSFTLZ9cjAbzRp FUSI7y9RRykgzLlizeq/vq4pAEKPtqH3/BNPVQXF288JZfyU18OWORNGHPvqDXD+E1r8 AfXw== X-Gm-Message-State: ACrzQf0l3/qv7uUUb8GrB4+3c3GWy3A4pGyxkeDrSRMeDN0TQSujR9RG TdLj72FuY9kMnnC4/SEz2pVxDQ== X-Google-Smtp-Source: AMsMyM7/L86aLkr8LkD3dYm3X3LClyki6UZleZRAocOrhXgEzwm1QCiP5WBx76/BBNeAAFLGsLBELw== X-Received: by 2002:a17:902:dad1:b0:17a:940:9c81 with SMTP id q17-20020a170902dad100b0017a09409c81mr9023378plx.93.1665218329981; Sat, 08 Oct 2022 01:38:49 -0700 (PDT) Received: from localhost.localdomain ([194.5.48.65]) by smtp.gmail.com with ESMTPSA id n1-20020a17090a2bc100b0020a0571b354sm2644371pje.57.2022.10.08.01.38.46 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 Oct 2022 01:38:49 -0700 (PDT) From: Zhangfei Gao To: Akhil Goyal , Declan Doherty , Fan Zhang , Ashish Gupta , Ray Kinsella Cc: dev@dpdk.org, acc@openeuler.org, Zhangfei Gao Subject: [PATCH resend v3 1/6] crypto/uadk: introduce uadk crypto driver Date: Sat, 8 Oct 2022 16:37:42 +0800 Message-Id: <20221008083747.6559-2-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221008083747.6559-1-zhangfei.gao@linaro.org> References: <20221008083747.6559-1-zhangfei.gao@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Introduce a new crypto PMD for hardware accelerators based on UADK [1]. UADK is a framework for user applications to access hardware accelerators. UADK relies on IOMMU SVA (Shared Virtual Address) feature, which share the same page table between IOMMU and MMU. Thereby user application can directly use virtual address for device dma, which enhances the performance as well as easy usability. This patch adds the basic framework. [1] https://github.com/Linaro/uadk Signed-off-by: Zhangfei Gao --- MAINTAINERS | 6 ++ doc/guides/cryptodevs/features/uadk.ini | 33 +++++++ doc/guides/cryptodevs/index.rst | 1 + doc/guides/cryptodevs/uadk.rst | 53 ++++++++++ drivers/crypto/meson.build | 1 + drivers/crypto/uadk/meson.build | 36 +++++++ drivers/crypto/uadk/uadk_crypto_pmd.c | 122 ++++++++++++++++++++++++ drivers/crypto/uadk/version.map | 3 + 8 files changed, 255 insertions(+) create mode 100644 doc/guides/cryptodevs/features/uadk.ini create mode 100644 doc/guides/cryptodevs/uadk.rst create mode 100644 drivers/crypto/uadk/meson.build create mode 100644 drivers/crypto/uadk/uadk_crypto_pmd.c create mode 100644 drivers/crypto/uadk/version.map diff --git a/MAINTAINERS b/MAINTAINERS index 5472fccf61..ed00b9afd1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1064,6 +1064,12 @@ M: Kai Ji F: drivers/crypto/scheduler/ F: doc/guides/cryptodevs/scheduler.rst +HiSilicon UADK crypto +M: Zhangfei Gao +F: drivers/crypto/uadk/ +F: doc/guides/cryptodevs/uadk.rst +F: doc/guides/cryptodevs/features/uadk.ini + Intel QuickAssist M: Kai Ji F: drivers/crypto/qat/ diff --git a/doc/guides/cryptodevs/features/uadk.ini b/doc/guides/cryptodevs/features/uadk.ini new file mode 100644 index 0000000000..df5ad40e3d --- /dev/null +++ b/doc/guides/cryptodevs/features/uadk.ini @@ -0,0 +1,33 @@ +; +; Supported features of the 'uadk' crypto driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +HW Accelerated = Y + +; +; Supported crypto algorithms of the 'uadk' crypto driver. +; +[Cipher] + +; +; Supported authentication algorithms of the 'uadk' crypto driver. +; +[Auth] + +; +; Supported AEAD algorithms of the 'uadk' crypto driver. +; +[AEAD] + +; +; Supported Asymmetric algorithms of the 'uadk' crypto driver. +; +[Asymmetric] + +; +; Supported Operating systems of the 'uadk' crypto driver. +; +[OS] +Linux = Y diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst index 39cca6dbde..cb4ce227e9 100644 --- a/doc/guides/cryptodevs/index.rst +++ b/doc/guides/cryptodevs/index.rst @@ -30,5 +30,6 @@ Crypto Device Drivers scheduler snow3g qat + uadk virtio zuc diff --git a/doc/guides/cryptodevs/uadk.rst b/doc/guides/cryptodevs/uadk.rst new file mode 100644 index 0000000000..a170224cac --- /dev/null +++ b/doc/guides/cryptodevs/uadk.rst @@ -0,0 +1,53 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright 2022-2023 Huawei Technologies Co.,Ltd. All rights reserved. + Copyright 2022-2023 Linaro ltd. + +UADK Crypto Poll Mode Driver +======================================================= + +UADK crypto PMD provides poll mode driver +All cryptographic operations are using UADK crypto API. +Hardware accelerators using UADK are supposed to be supported. + + +Features +-------- + +UADK crypto PMD has support for: + + +Test steps +----------- + + .. code-block:: console + + 1. Build + cd dpdk + mkdir build + meson build (--reconfigure) + cd build + ninja + sudo ninja install + + 2. Prepare + echo 1024 > /sys/devices/system/node/node0/hugepages/hugepages-2048kB/nr_hugepages + echo 1024 > /sys/devices/system/node/node1/hugepages/hugepages-2048kB/nr_hugepages + echo 1024 > /sys/devices/system/node/node2/hugepages/hugepages-2048kB/nr_hugepages + echo 1024 > /sys/devices/system/node/node3/hugepages/hugepages-2048kB/nr_hugepages + mkdir -p /mnt/huge_2mb + mount -t hugetlbfs none /mnt/huge_2mb -o pagesize=2MB + + 3. Run test app + +Dependency +------------ + +UADK crypto PMD relies on UADK library [1] + +UADK is a framework for user applications to access hardware accelerators. +UADK relies on IOMMU SVA (Shared Virtual Address) feature, which share +the same page table between IOMMU and MMU. +As a result, user application can directly use virtual address for device dma, +which enhances the performance as well as easy usability. + +[1] https://github.com/Linaro/uadk diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build index 147b8cf633..ee5377deff 100644 --- a/drivers/crypto/meson.build +++ b/drivers/crypto/meson.build @@ -18,6 +18,7 @@ drivers = [ 'octeontx', 'openssl', 'scheduler', + 'uadk', 'virtio', ] diff --git a/drivers/crypto/uadk/meson.build b/drivers/crypto/uadk/meson.build new file mode 100644 index 0000000000..dda6c6b257 --- /dev/null +++ b/drivers/crypto/uadk/meson.build @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2022-2023 Huawei Technologies Co.,Ltd. All rights reserved. +# Copyright 2022-2023 Linaro ltd. + +if not is_linux + build = false + reason = 'only supported on Linux' + subdir_done() +endif + +if arch_subdir != 'arm' or not dpdk_conf.get('RTE_ARCH_64') + build = false + reason = 'only supported on aarch64' + subdir_done() +endif + +sources = files( + 'uadk_crypto_pmd.c', +) + +deps += 'bus_vdev' +dep = cc.find_library('libwd_crypto', required: false) +if not dep.found() + build = false + reason = 'missing dependency, "libwd_crypto"' +else + ext_deps += dep +endif + +dep = cc.find_library('libwd', required: false) +if not dep.found() + build = false + reason = 'missing dependency, "libwd"' +else + ext_deps += dep +endif diff --git a/drivers/crypto/uadk/uadk_crypto_pmd.c b/drivers/crypto/uadk/uadk_crypto_pmd.c new file mode 100644 index 0000000000..ec9bb174c7 --- /dev/null +++ b/drivers/crypto/uadk/uadk_crypto_pmd.c @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2022-2023 Huawei Technologies Co.,Ltd. All rights reserved. + * Copyright 2022-2023 Linaro ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +enum uadk_crypto_version { + UADK_CRYPTO_V2, + UADK_CRYPTO_V3, +}; + +struct uadk_crypto_priv { + enum uadk_crypto_version version; +} __rte_cache_aligned; + +static uint8_t uadk_cryptodev_driver_id; + +RTE_LOG_REGISTER_DEFAULT(uadk_crypto_logtype, INFO); + +#define UADK_LOG(level, fmt, ...) \ + rte_log(RTE_LOG_ ## level, uadk_crypto_logtype, \ + "%s() line %u: " fmt "\n", __func__, __LINE__, \ + ## __VA_ARGS__) + +static struct rte_cryptodev_ops uadk_crypto_pmd_ops = { + .dev_configure = NULL, + .dev_start = NULL, + .dev_stop = NULL, + .dev_close = NULL, + .stats_get = NULL, + .stats_reset = NULL, + .dev_infos_get = NULL, + .queue_pair_setup = NULL, + .queue_pair_release = NULL, + .sym_session_get_size = NULL, + .sym_session_configure = NULL, + .sym_session_clear = NULL, +}; + +static int +uadk_cryptodev_probe(struct rte_vdev_device *vdev) +{ + struct rte_cryptodev_pmd_init_params init_params = { + .name = "", + .private_data_size = sizeof(struct uadk_crypto_priv), + .max_nb_queue_pairs = + RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS, + }; + enum uadk_crypto_version version = UADK_CRYPTO_V2; + struct uadk_crypto_priv *priv; + struct rte_cryptodev *dev; + struct uacce_dev *udev; + const char *name; + + udev = wd_get_accel_dev("cipher"); + if (!udev) + return -ENODEV; + + if (!strcmp(udev->api, "hisi_qm_v2")) + version = UADK_CRYPTO_V2; + + free(udev); + + name = rte_vdev_device_name(vdev); + if (name == NULL) + return -EINVAL; + + dev = rte_cryptodev_pmd_create(name, &vdev->device, &init_params); + if (dev == NULL) { + UADK_LOG(ERR, "driver %s: create failed", init_params.name); + return -ENODEV; + } + + dev->dev_ops = &uadk_crypto_pmd_ops; + dev->driver_id = uadk_cryptodev_driver_id; + dev->dequeue_burst = NULL; + dev->enqueue_burst = NULL; + dev->feature_flags = RTE_CRYPTODEV_FF_HW_ACCELERATED; + priv = dev->data->dev_private; + priv->version = version; + + rte_cryptodev_pmd_probing_finish(dev); + + return 0; +} + +static int +uadk_cryptodev_remove(struct rte_vdev_device *vdev) +{ + struct rte_cryptodev *cryptodev; + const char *name; + + name = rte_vdev_device_name(vdev); + if (name == NULL) + return -EINVAL; + + cryptodev = rte_cryptodev_pmd_get_named_dev(name); + if (cryptodev == NULL) + return -ENODEV; + + return rte_cryptodev_pmd_destroy(cryptodev); +} + +static struct rte_vdev_driver uadk_crypto_pmd = { + .probe = uadk_cryptodev_probe, + .remove = uadk_cryptodev_remove, +}; + +static struct cryptodev_driver uadk_crypto_drv; + +#define UADK_CRYPTO_DRIVER_NAME crypto_uadk +RTE_PMD_REGISTER_VDEV(UADK_CRYPTO_DRIVER_NAME, uadk_crypto_pmd); +RTE_PMD_REGISTER_CRYPTO_DRIVER(uadk_crypto_drv, uadk_crypto_pmd.driver, + uadk_cryptodev_driver_id); diff --git a/drivers/crypto/uadk/version.map b/drivers/crypto/uadk/version.map new file mode 100644 index 0000000000..c2e0723b4c --- /dev/null +++ b/drivers/crypto/uadk/version.map @@ -0,0 +1,3 @@ +DPDK_22 { + local: *; +}; -- 2.36.1